Maximizing the Potential of Custom RISC-V Vector Extensions for Speeding up SHA-3 Hash Functions
Huimin Li (TU Delft - Electrical Engineering, Mathematics and Computer Science)
Nele Mentens (Katholieke Universiteit Leuven, Universiteit Leiden)
Stjepan Picek (Radboud Universiteit Nijmegen, TU Delft - Electrical Engineering, Mathematics and Computer Science)
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Abstract
SHA-3 is considered to be one of the most secure standardized hash functions. It relies on the Keccak-f[1 600] permutation, which operates on an internal state of 1 600 bits, mostly represented as a 5 x 5 x 64-bit matrix. While existing implementations process the state sequentially in chunks of typically 32 or 64 bits, the Keccak-f[1 600] permutation can benefit a lot from speedup through parallelization. This paper is the first to explore the full potential of parallelization of Keccak-f[1 600] in RISC-V based processors through custom vector extensions on 32-bit and 64-bit architectures. We analyze the Keccak $\mathbf{f}[1 \ 600]$ permutation, composed of five different step mappings, and propose ten custom vector instructions to speed up the computation. We realize these extensions in a SIMD processor described in System Verilog. We compare the performance of our designs to existing architectures based on vectorized application-specific instruction set processors (ASIP). We show that our designs outperform all related work in throughput due to our carefully selected custom vector instructions.