Edge-prediction DTC and Clock-gating TDC Design for Ultra Low Power All Digital PLL

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Edge-prediction DTC and Clock-gating TDC Design for Ultra Low Power All Digital PLL

Master Thesis (2014)

Author(s)

B. Wang

Contributor(s)

R.B. Staszewski – Mentor

Y.H. Liu – Mentor

Copyright

DTC CMOS TDC ADPLL Ultra-low power

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https://resolver.tudelft.nl/uuid:ea10ff84-a257-4712-b9ab-8cdf13b23a4d

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Publication Year

2014

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