A 40-Gb/s 2¹¹-1 PRBS with Distributed Clocking and a Trigger Countdown Output

Abstract

A 2¹¹-1 pseudo-random binary sequence (PRBS) generator with trigger synchronization output (9.77-MHz rate) is implemented using synthetic transmission lines for the clock distribution. The full-rate data sequence is sourced from a 2:1 multiplex of dual shift register outputs synchronized to a half-rate clock. Quadrature half-rate clocks generated by a dual-mode (Dynastat) divide-by-2 are distributed via the synthetic lines to optimize power-speed tradeoffs in the design. The 790×620μm² PRBS designed in 130-nm SiGe BiCMOS (200/280 GHz f_T/fmax) consumes 250 mA at 2.5 V (i.e., 625 mW).