A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW

Conference paper (2018)

Authors

Tsung Hsien Tsai Taiwan Semiconductor Manufacturing Company (TSMC)
Ruey-Bin Sheen Taiwan Semiconductor Manufacturing Company (TSMC)
Chih Hsien Chang Taiwan Semiconductor Manufacturing Company (TSMC)
R.B. Staszewski University College Dublin
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Published Date

22-10-2018

Language

English

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Abstract

All-digital PLLs (ADPLL) based on a ring-oscillator (RO) provide very fast settling, but they suffer from quantization (Q) noise due to discrete tuning of their digitally controlled oscillator (DCO). Although RO charge-pump PLLs (CP-PLL) do not exhibit Q-noise thanks to their continuous VCO tuning, they are quite slow and require huge VCO gain. We propose a hybrid-PLL in 7nm FinFET CMOS that combines the best advantages of ADPLL and CP-PLL with a periodical phase realignment by the reference clock. It covers 0.2GHz-4GHz with 0.619ps integrated jitter and settles in 0.6us.