A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW

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A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW

Conference Paper (2018)

Author(s)

Tsung-Hsien Tsai (Taiwan Semiconductor Manufacturing Company (TSMC))

Ruey-Bin Sheen (Taiwan Semiconductor Manufacturing Company (TSMC))

Chih-Hsien Chang (Taiwan Semiconductor Manufacturing Company (TSMC))

Robert Bogdan Staszewski (University College Dublin)

Affiliation

External organisation

DOI related publication

https://doi.org/10.1109/VLSIC.2018.8502274 Final published version

To reference this document use

https://resolver.tudelft.nl/uuid:fcc56d78-212b-4a78-a868-5b9d23044176

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Publication Year

2018

Language

English

Affiliation

External organisation

Volume number

2018-June

Article number

8502274

Pages (from-to)

183-184

ISBN (electronic)

978-1-5386-4214-6

Event

2018 Symposia on VLSI Technology and Circuits (2018-06-18 - 2018-06-22), Hilton Hawaiian Village, Honolulu, United States

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138

Abstract

All-digital PLLs (ADPLL) based on a ring-oscillator (RO) provide very fast settling, but they suffer from quantization (Q) noise due to discrete tuning of their digitally controlled oscillator (DCO). Although RO charge-pump PLLs (CP-PLL) do not exhibit Q-noise thanks to their continuous VCO tuning, they are quite slow and require huge VCO gain. We propose a hybrid-PLL in 7nm FinFET CMOS that combines the best advantages of ADPLL and CP-PLL with a periodical phase realignment by the reference clock. It covers 0.2GHz-4GHz with 0.619ps integrated jitter and settles in 0.6us.