Design of a SAR ADC in 2 µm Silicon Carbide CMOS Technology

Abstract

Silicon carbide (SiC) is a wide-bandgap semiconductor with excellent resistance to harsh environments, making it well-suited for high-temperature electronics. Due to its similarities to silicon, silicon carbide processing for CMOS can leverage existing silicon manufacturing methods. However, SiC CMOS production remains in early development and requires robust, conservative circuit design. This thesis presents the design and simulation of an eight-bit analog-to-digital converter (ADC) targeted for operation up to 500 °C. Simulations without mismatch modeling predict a maximum integral and differential nonlinearity of less than 0.3 LSB, and an effective resolution of 7.89 bits at 200 °C. The ADC is to be fabricated in a 2 µm SiC CMOS process developed by Fraunhofer IISB. If measurement results validate the design, this ADC would represent the highest-resolution monolithically integrated ADC demonstrated above 300 °C. In addition to the ADC design, measurements of SiC CMOS logic gates show low fabrication yield, contrary to previous measurements of Fraunhofer IISB SiC CMOS circuits. Failure analysis attributed this to defects in the metallization layers.