SiC Bandgap Reference Design for High-Temperature Environments

Abstract

Harsh-environment systems such as electrified powertrains, aircraft actuators, deep-well instrumentation, and space electronics increasingly require analog circuits that operate close to the hot zone. 4H-silicon carbide (4H-SiC) CMOS technology can operate at temperatures far beyond the limits of silicon, but precision analog design in this technology is constrained by an immature design environment: the Fraunhofer IISB 4H-SiC CMOS PDK used in this work provides MOSFET and resistor models but no bipolar-transistor compact model, no process corners, and no Monte Carlo support. This thesis addresses the design of an on-chip voltage reference — the block that sets the absolute accuracy of data converters, sensor interfaces, and bias circuits — under exactly these constraints.

The thesis develops a bandgap-style reference for 25 ◦C to 450 ◦C operation through a model-aware methodology. First, the available 4H-SiC NMOS and PMOS devices are characterized over temperature and the BSIM4SIC compact model is audited against measured tapeout data. The audit shows that the NMOS threshold-voltage temperature slope is well reproduced, whereas the PMOS threshold magnitude (up to 1 V error at 500 ◦C), the PMOS current drive, the simulated NMOS high-temperature current rolloff, and the PMOS off-state leakage (measured 1.23 𝜇A against simulated picoamperes) are not reliable. The subthreshold region is identified as the weakest validated model region. Based on this evidence, MOSFETs are restricted to current-copying, biasing, and startup roles, and the reference-defining temperature behavior is assigned to the process SiC p-n diode, characterized from 24 to 625 ◦C, and to PolySi resistors, characterized to 600 ◦C.
The proposed circuit is a diode-assisted current-mode reference: a resistor-defined branch sets a bias current, a cascoded PMOS mirror copies it at unity ratio, and the reference output sums the diode CTAT voltage with the copied current converted through a gain-setting PolySi resistor. A startup circuit removes the zero-current state. At schematic level, the no-trim circuit achieves an average reference voltage of 2.597 V with a box-method temperature coefficient of 123 ppm/
◦C over 25–450 ◦C at a 20 V supply, a maximum untrimmed deviation of 2.82%, and 0.797–3.439 mW power dissipation — roughly an order of magnitude below reported measured SiC reference benchmarks. The simulated drift lies
within the measured spread of published SiC CMOS references. The main limitations are quantified rather than hidden: low-frequency PSRR of 13.6–16.5 dB, line regulation of 146.5–207.8 mV/V, and a high-temperature output upturn driven by the second-order temperature coefficient of the gain resistor. A complete layout with common-centroid mirrors, segmented resistors, and matched diodes passed the design-rule check; layout-versus-schematic closure is blocked by the custom SiC diode device and is identified, together with supply isolation, curvature compensation, statistical verification, and silicon measurement, as the necessary future work.