Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions

Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions

Wu, L. (TU Delft Computer Engineering)

Hamdioui, S. (promotor)
Taouil, M. (copromotor)

Delft University of Technology

2021-02-22

As STT-MRAM mass production and deployment in industry is around the corner, high-quality yet cost-efficient manufacturing test solutions are crucial to ensure the required quality of products being shipped to end customers. This dissertation focuses on STT-MRAM testing, covering three abstraction levels: manufacturing defects, fault models, and test solutions. We apply the advanced device-aware test (DAT) approach to STT-MRAM defects, including resistive defects on interconnects and STT-MRAM device-internal defects such as pinhole defects, synthetic anti-ferromagnet flip defects, intermediate state defects. With the derived accurate defect models calibrated by silicon data, a comprehensive fault analysis based on SPICE circuit simulations is performed. STT-MRAM unique faults are identified, including both permanent faults and intermittent faults. Based on the obtain fault models, high-quality test solutions are proposed. Additionally, this dissertation also explores the impact of magnetic coupling and density on STT-MRAM performance for robust designs.

memory test
device-aware test
manufacturing test
STT-MRAM
MTJ
manufacturing defect
fault model
robust design
magnetic coupling

https://doi.org/10.4233/uuid:088a3991-4ea9-48a0-9b92-cc763748868c

978-94-6384-199-3

Institutional Repository

doctoral thesis

© 2021 L. Wu