Design and Qualification of a High-Speed Low-Power Comparator in 40 nm CMOS Technology

Design and Qualification of a High-Speed Low-Power Comparator in 40 nm CMOS Technology

Mohammad Zaki, A.R. (TU Delft Electronic Instrumentation)
Du, Yutong (Student TU Delft)
Nihtianova, S. (TU Delft Electronic Instrumentation)

2023

This paper presents the design methodology, test setup and experimental qualification results of a high-speed low-power threshold comparator in 40 nm CMOS technology intended for the registry of particles landing on a PIN-detector surface in particle detector readout electronics. The operation of the designed comparator is experimentally qualified for ideal digital pulses and analog signals generated by the preceding stages in a targeted potential application.

high-speed
low-power
readout interface
voltage comparator
temperature sensor

http://resolver.tudelft.nl/uuid:137ec7f4-d2bc-4c3d-9c22-6ef1610d5640

https://doi.org/10.1109/ET59121.2023.10278935

IEEE

2024-04-17

979-8-3503-0201-1

2023 32nd International Scientific Conference Electronics, ET 2023 - Proceedings

2023 XXXII International Scientific Conference Electronics (ET), 2023-09-13 → 2023-09-15, Sozopol, Bulgaria

2023 32nd International Scientific Conference Electronics, ET 2023 - Proceedings

Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

Institutional Repository

conference paper

© 2023 A.R. Mohammad Zaki, Yutong Du, S. Nihtianova