Compact Neural Amplifier for Next-Generation Brain-Machine Interfaces

Master thesis (2022)

Authors

M. Exalto Electrical Engineering, Mathematics and Computer Science

Contributors

D.G. Muratore Bio-Electronics - EEMCS (mentor)
Faculty
Electrical Engineering, Mathematics and Computer Science, Electrical Engineering, Mathematics and Computer Science
Copyright: © 2022 Marvin Exalto
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Published Date

12-07-2022

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Abstract

Brain-machine interfaces (BMI) are electronic devices that form an interconnection between the users brain and an external device through which the user can control the device and the device can apply stimulation to the users brain or nervous system. BMIs have undergone a rapid evolution in development and applications. While the first generation of BMI were exclusively used as proof of concept in research experiments, now more and more clinical applications in humans are becoming a reality. In recent years, various neurodegenerative diseases such as locked-in syndrome, epilepsy and retinitis pigmentosa, for which there currently exist no cures, have been successfully treated using implantable BMIs.

BMI development is continuously striving towards increasing the recording resolution and number of recording channels. As a result of recent innovations in electrode design and implementation, the recording of single brain cells has become possible, enabling the development of BMI with single-cell recording resolution. The primary bottleneck preventing more recording channels in single-cell resolution BMIs is caused by the neural amplifiers required to amplify the neural signals from the electrodes. Large amounts of recording channels require large arrays of neural amplifiers which in turn require large chip area and power, both of which are resources that are limited in implantable BMI applications.

The primary focus of this work is the development of a neural amplifier for use in next-generation single-cell resolution BMI. The neural amplifier is developed in 40nm CMOS technology and exploits the spatial correlation of the neural signal to implement a novel sharedfeedback system that reduces the power and area per recording channel. The amplifier is designed and verified with post-layout simulations, achieving a gain of 45 dB over a bandwidth from 93.8Hz to 5.44kHz, power usage of 600 nW per recording channel and an input referred noise voltage of 9.00 μVrms with a total chip area of 2190 μm2 per recording channel.