This thesis analyzes and describes a wearable pressure sensor to detect intraocular pressure and guide clinician diagnosis of glaucoma. Although glaucoma has many symptoms and risk factors, high intraocular pressure is the most predominant. A method to continuously and accurately record intraocular pressure measurements and fluctuations in a patient could lead to a more reliable glaucoma diagnosis and a better understanding of glaucoma progression. The proposed sensor consists of an ecoflex dielectric layer, between two graphene-silver nanowire spiral antenna electrodes which also act as the membrane structure. The sensor deflection depends on the intraocular pressure fluctuations; higher pressure leads to larger deflection values, therefore, larger capacitance change. The capacitance change leads to a shift of the resonant frequency, which is simulated in this thesis. The sensor must be smaller than 11 mm2 to fit on a commercial lens. Specifically, this thesis analyzes and simulates the effects of electrode thickness and shape on the overall performance of the sensor. The optimum geometry of the capacitive sensor is analyzed to maximize sensor sensitivity and quality factor, with a correlated frequency appropriate for a wearable lens. Using Computer Simulation Technology, the optimized antenna dimensions are spiral-electrodes with a plate thickness of 350µm, and 3 spiral revolutions; leading to an increase in sensitivity of 1.4 MHz/mmHg.

This report details the design and development of an agar/NaCl gel-like tissue phantom mimicking the electrical properties of wet human skin. The skin phantom provides a reliable, reproducible testing ground for dry-contact polydimethylsiloxane (CNT/PDMS) electrodes, with the aim of recording electroencephalograms (EEGs) and stimulating brain activity in a controlled environment. These electrodes are being designed for the development of an in-ear brain-computer interface (BCI). The electrical properties of biological tissue are referred to as the conductivity σ and permittivity ε and denote the ability for a material to conduct and trap electric charge respectively. These properties are frequency dependent and particularly for EEGs, a frequency range of 1-1000 Hz is of interest (with some added leeway). Wet skin hereby has a conductivity of around 0.1 Siemens to 0.2 Siemens in the 1-1000 Hz frequency range whereas the permittivity ranges from 5.7 * 10^5 to 5.2 * 10^5. Different agar and agar/NaCl solutions are created to try and obtain solutions with the mentioned electric properties. Specifically, NaCl is added to improve the conductivity and obtain a non-linear frequency response similar to that of human skin. The electrical properties of the phantoms were verified/measured using the parallel plate method. This method is essentially sandwiching a material under test (MUT) (in this case the fabricated gel-like agar and agar/NaCl solutions) between two conducting plates. This method is most suited for measurements in the lower frequency spectrum. The skin phantom consisting of 3.04 mass fraction weight (wt.%) agar and 0.539 wt.% NaCl shows the closest similarity to the conductivity of wet skin. Namely, a conductivity of ~ 0.1 Siemens to 0.45 Siemens in the frequency range of 1-1000 Hz. A decrease of 0.250 wt.% NaCl will most likely achieve the desired conductivity response of 0.1 Siemens to 0.2 Siemens in the frequency range of 1-1000 Hz. The skin phantom consisting of 3.00 wt.% agar and 1.02 wt.% NaCl showed the permittivity closest to that of wet skin, but might have been a noisy outlier. Its permittivity ranges from 10 * 10^6 and 7.5 * 10^6. This is still a large error margin from the desired 5.7 * 10^5 to 5.2 * 10^5. Additional fillers like glycine or Al powder need to be added to the solutions to obtain a permittivity close to that of wet human skin. Multi-day and difference in applied pressure measurements are performed to check the sensitivity and reproducibility of the phantoms. Applied pressure hereby has little to no influence whereas a longer life-span of the fabricated phantom shows a drastic decrease of the electrical properties of the phantoms after day 1. The changes then seem to settle. Worth mentioning is that the change is only drastic when the solution has a high conductivity. This is generally not the case for solutions with conductivities close to wet skin.

This bachelor end project thesis is describing ways to use dry-electrode electroencephalography (EEG) measurements for authentication. There are five proposed methods based on the literature study, which in this report are called: ’frequency tagging’, ’pseudowords’, ’familiar music’, ’mental tasks’, and ’emotions’. First, all methods were tested, however, this proved too much work to perform each of them thoroughly and wellbounded, so two were selected for further investigation. For the method involving frequency tagging, experiments were done and the obtained data was used to extract features. This analysis showed that tagging can be discovered in the EEG data, but re-induction of tagged words was hard to achieve, which would make it difficult to create an authentication system reliant on it. Analyzing results from experiments to test the pseudoword method was more promising. Some similarities between the features that were expected from papers and features from our results were found. These features were therefore used for classification, and resulted in small improvements in accuracy. This accuracy did however vary a lot between different data sets.

Currently, EEG recordings are mostly made using scalp recording devices. These devices are typically difficult to put on and bulky, limiting their use to a lab environment. In-ear EEG recording is proposed as a more practical alternative to scalp EEG recording. In-ear EEG replaces the scalp electrode array with more discrete earpieces, recording the EEG signals from the ear canal instead of the scalp. Because of their increased convenience with respect to their scalp electrode array counterpart, the earpieces allow for everyday use, enabling the possibility of long-term EEG recording, outside of a lab environment. This work presents the design of a fully-integrated in-ear EEG device. The device has been designed to record EEG signals, process them locally, and transmit the processed data to a smartphone or personal computer. The device is made to be easily re-programmable, making it possible to change the device firmware depending on the intended application. This functionality has been integrated into a small form factor, to allow for the integration of the electronics into an earpiece. A low-power design has been created, to allow for long-term battery operation. Two prototypes have been made. The first prototype focuses on exploring different system configurations, with the small form factor less of a priority. The performance of the prototype is tested by comparing it to a commercially available scalp EEG recording device based on scalp EEG recordings. For this comparison, the auditory steady-state response (ASSR), steady-state visual evoked potential (SSVEP), and alpha-band modulation paradigms are used. The prototype has shown similar performance to the scalp EEG device in these experiments, with the scalp EEG device performing slightly better for the ASSR and alpha-band modulation paradigms, while the prototype showed the best performance for the SSVEP paradigm. The second prototype realises the best-performing system configuration that has been found with the first prototype into a form factor that fits into an earpiece. Ear EEG experiments are performed, with electrodes placed around the ears. The ASSR, SSVEP, and alpha-band modulation paradigms have again been used in these experiments. The measured performance on the ASSR and alpha-band modulation paradigms are slightly worse than that measured using the scalp EEG experiments. The SSVEP experiments showed significantly worse performance compared to the scalp EEG experiments. These results align with the expectations, as ear EEG has been documented to have performance close to scalp EEG for the ASSR and alpha-band modulation paradigms, while the SSVEP performance is typically worse for ear EEG than for scalp EEG.

In-ear EEG is a discreet and convenient method for monitoring EEG by placing the electrodes in the ear canal. This enables everyday monitoring outside of clinical environments in contrast to generally used scalp EEG with wet electrodes. This thesis proposes and describes the design of novel flexible dry CNT/PDMS electrodes with short pins, long pins, and a snake pattern. These dry electrodes make use of microstructures to improve electrode-skin impedance (ESI) by enlarging the effective contact area. In the composite fabrication process, SEM is used to optimize CNT dispersion which plays a significant role in the impedance of the material. The performance of the proposed dry electrodes is evaluated in comparison to conventionally used wet Ag/AgCl electrodes. Electrode impedance measurements show the superior performance of CNT/PDMS electrodes with microstructures with lower aspect ratios. This is confirmed by ESI measurements, which show a 49 % improvement at 10 Hz for the electrode with short pins compared to the electrode with long pins, and a further 53 % improvement for electrodes with the snake pattern. This makes the latter comparable to wet electrodes. Moreover, normalization by the projected surface area shows significantly lower ESI at low frequencies for dry CNT/PDMS electrodes with a snake pattern compared to wet electrodes. ESI of the dry electrode at 10 Hz is 30 kΩ cm2, one order of magnitude lower than for wet electrodes. At 1 kHz the ESI is 9.9 kΩ cm2, which is comparable to wet electrodes. Finally, ASSR tests show comparable suitability of dry CNT/PDMS electrodes and wet electrodes for in-ear EEG monitoring, suggesting that the proposed dry CNT/PDMS electrodes are a viable solution for in-ear EEG applications.

Class-D amplifiers are quickly becoming the standard in many audio applications. Their highly efficient behavior and wide power range make these amplifiers more suitable than traditional Class A/AB audio amplifiers. Battery-powered devices are a particularly interesting sub-field due to their special demand for extended battery duration and higher efficiency. An output power lower than 2 W, along with good performances in terms of linearity and efficiency, is often required. Many stand-alone Class-D Amplifiers have analog inputs, making them susceptible to interference that negatively impacts their behavior. This problem can be mitigated by employing an insensitive input digital interface. Many standard solutions often require complex architectures, which limit these systems' reliability. This work proposes a digital-input class-D amplifier with a multi-level output stage that, together with a relatively low (480 kHz) switching frequency, reduces idle power consumption while achieving good linearity. Based on a 180 nm BCD technology, it can drive a 16-Ω load showing pre-layout simulated performances: -111.3 dB THD+N, 115.6 DR, 91.4 % peak efficiency, and 2.14 mW idle power consumption.

This thesis presents the design of a low-power, sub-1V, BJT-based temperature sensor. It is based on a capacitively-biased (CB) BJT front-end, in which capacitors are discharged across diode-connected BJTs to obtain proportional-to-temperature (PTAT) and complementary-to-temperature (CTAT) voltages. These voltages are then digitised by a switched-capacitor Delta-Sigma Modulator (DSM), which employs energy-efficient inverter-based amplifiers that can operate from a sub-1V supply. To mitigate the effects of component mismatch and 1/f noise, dynamic error-cancellation techniques such as chopping, auto-zeroing and dynamic element matching are used in both the front-end and the DSM. After a 1-point temperature calibration, the sensor achieves a simulated inaccuracy of ±0.20oC (3σ) over temperatures ranging from -55oC to 125oC. From simulations, it does this while operating from a 0.9V supply and dissipating only 270nW. It occupies an estimated area of 0.09mm2 in a 180nm CMOS process. Compared to previous CB temperature sensors, this design occupies 2.8x smaller area and dissipates 3x less power.

To achieve greater specificity in neurostimulation, bidirectional neural interfaces are required to verify the recorded neural response after stimulation. The specific neural interface targeted in this thesis is the epiretinal implant. Due to the heterogeneity of the retinal ganglion cells (RGCs), high-fidelity vision is only possible when all the types of RGCs near the neurostimulator are mapped. This necessitates the bidirectionality of the implant and poses significant difficulties, as large stimulation artifacts obscure the small neural response that needs to be recorded. Furthermore, in order to cover a large area of the retina, a channel count in the order of 104 will be required. Scaling existing neurostimulators would lead to chips that are >30mm2, which is too large. The aim of this thesis is therefore to design a neurostimulator for the epiretinal implant that is capable of implementing artifact-reducing algorithms, and is smaller than the current state-of-the-art. The proposed system makes use of a mismatch-based digital-to-analog converter (DAC), and has been optimized for an output range of 0-6 μA at an effective resolution of 8-bits. Furthermore, in order to decrease the amount of stimulation units required, waveform interleaving has been proposed, where the anodic and cathodic stimulator are separated. A voltage compliance monitor is also designed to ensure proper stimulation output. The designed system has been fabricated and occupies 0.0003mm2 for two channels. Scaling this directly to 104 channels would result in an area of 1.645mm2. This area can be reduced even further via electrode multiplexing, which the designed system readily allows for. An output availability (i.e. how many input codes are possible after calibrating) of 99.2% and 97.3% is reported for the anodic and cathodic stimulator at an 8-bit resolution over the full output range.

This thesis describes the design of a 3rd order 1-bit delta-sigma modulator whose input-signal range (0 to 1.95V) exceeds its supply voltage (1.2V). By using a passive input stage and a single-OTA resonator, this beyond-the-rails modulator realizes a 3rd order loop filter with only two amplifiers instead of the usual three and thus achieves state-of-the-art energy efficiency. Realized in a standard TSMC 65nm CMOS technology, the modulator achieves 99.24dB SNR, 99.2dB SNDR and 100dB DR in a bandwidth of 24kHz while consuming only 80μW. This translates into the highest energy efficiency (FoMSNDR, 184dB) reported for a continuous-time delta-sigma modulator.

Abstract—This paper investigates the performance of commonly used spike detection algorithms (Absolute Amplitude Thresholding and Non-linear Energy Operator) on compressed neural signals using a novel wired-OR lossy compression algorithm. Performing compression with the wired-OR architecture mainly removes the noisy baseline and preserves spikes in the neural signal. As a result, the spike detection sensitivity and accuracy improve or stay similar after compression. In addition, this paper proposes a new spike detection algorithm, the non-zero spike detector, that can be efficiently integrated into hardware with the wired-OR compression scheme. By using a firing rate-based approach to optimize the threshold in the non-zero spike detector, the proposed technique outperforms both Absolute Amplitude Thresholding and the Non-linear Energy Operator across different signal-to-noise ratios and firing rates. The wired-OR readout architecture, in combination with the non-zero spike detector, is a promising approach to achieve massive compression while preserving the neural signal and maintaining spike detection performance.

This thesis describes the design and simulation of a capacitively-coupled autozeroed and chopped operational amplifier in the TSMC high-voltage BCD 0.18 μm 5 V technology. It uses chopping and autozeroing to achieve high precision (10 μV offset and 50 nV/√Hz noise density) and a capacitively-coupled input stage to safely handle beyond-the-rails 50 V input voltages. The amplifier employs a pseudo-continuous time architecture that periodically autozeroes a single signal path, which is also chopped. Compared to amplifiers with ripple-reduction loops, this approach should potentially result in area and power savings. However, it also means that the signal path is periodically broken during a short deadtime, during which the signal path is autozeroed. Since the presence of the deadtime comes with a noise penalty, the amplifier’s clocking scheme has been optimized to reduce the length of the deadtime relative to the length of the two amplification phases. The simulated performance of the resulting amplifier is comparable with that of other precision amplifiers, while its chip area should be lower, resulting in lower production costs.

An artificial retina can replace some of the functionality of the eye in people that have experienced partial or complete loss of vision. Loss of vision is associated with many negative effects in one’s life and can be a debilitating condition. Artificial retinas in the form of a chip thus offer the potential to greatly improve people’s lives. A wireless implementation is much preferred to the wired alternative, as it reduces the risks associated with implantable devices while also being less invasive to the patient. Wirelessly powering an artificial retina implant requires careful consideration of the impact on tissue heating as this is the fundamental limit in how much power an implantable device can consume. This thesis provides an optimal implementation of wireless power transfer in the framework of an artificial retina implant with the explicit goal of reducing tissue heating. A literature study forms the basis for identifying the key metrics and providing a switched capacitor power converter (SCPC) topology needed to realise the final system performance. The key innovations are a first-of-its-kind design of an ctive rectifier, a novel system-level optimisation and an SCPC to implement the o ptimised system approach while simultaneously enabling a novel, efficient, low-overhead closed-loop control of the link. It was shown that a 30 % reduction in radiated power can be realised for a given system while maintaining the same output load power. The designed active rectifier can achieve orders of magnitude faster settling compared to the state of the art, allowing rapid amplitude-shift keyed data transfer to be employed on the wireless power transfer link. The active rectifier achieves a simulated voltage conversion ratio of 92.0 % and a power conversion efficiency of 90.1 % for a 500 Ω load. an SCPC as designed and fabricated to achieve a load transformation to the calculated optimum load. A simulated 80 % efficiency at a power density of 29 mW/mm2 was achieved, with a conversion range of 0.7 − 1.8. Measurement results proved to be inconclusive. The SCPC was shown not to work and the active rectifier’s performance couldn’t be precisely verified. An improved measurement setup and additional debugging options in the chip design are among the proposed improvements for future work.

Quantum computing offers exponential speed-up for problems that are computationally intractable with classical computing. However, quantum processors with thousands to millions of quantum bits (qubits) are needed. Room-temperature electronics are used to control and readout today's qubits operating at cryogenic temperature. As the number of wires that can be placed between room temperature and the cryogenic chamber is limited, this creates a bottleneck in the scaling of quantum computers. Cryogenic CMOS (cryo-CMOS) electronics has been proposed to overcome this bottleneck. Operating the control electronics at cryogenic temperature, very close to the qubit, and controlling and reading out the qubits by frequency multiplexing relaxes the interconnect bottleneck. This work tackles this challenge by focusing on the qubit readout system and more specifically on the spin-qubit readout. The main target is to develop a cryo-CMOS analog-to-digital converter (ADC) for such an application.  The readout of frequency multiplexed spin-qubits using RF reflectometry is considered the target application. The non-idealities of the RF-reflectometry scheme are simulated and analyzed for the qubit multiplexing and included in the system-level modeling of the readout chain. The target design specifications of the ADC are derived from such system-level simulations, resulting in the need for a 1 GSa/s ADC with ENOB > 6 bits operating at 4 K for the readout ~20 frequency-multiplexed spin-qubits with a BER of 1e-03. Based on those specifications, this work proposes a 2-channel time-interleaved ADC using a Loop-Unrolled Successive Approximation Register (LU-SAR) ADC. The loop unrolling technique in combination with time-interleaving achieves the sampling rate of 1.1 GSa/s. The design includes the integration of a dynamic amplifier as an input driver and the generation of all required timing for the ADC core and the dynamic amplifier. Foreground calibration of the SAR comparator offset is included to achieve the linearity specifications. The ADC has been designed in TSMC 40nm CMOS technology and taped out for fabrication. After  calibration of comparator offset and calibration of the delay/gain mismatch between the two time-interleaved channels, the simulated performance of the ADC demonstrates an ENOB of 6.35 bits, SNDR of 40 dB, SFDR >50 dBc. The Figure-of-Merit of the designed ADC is 25.2 fJ/conv at 1 GSa/s sampling rate (including the driving amplifier and the clocking circuitry), which is significantly higher than the prior cryogenic ADCs and on-par with room-temperature state-of-the-art ADCs. The proposed ADC contributes towards the realization of future large-scale quantum computers, comprising million-qubit quantum processors integrated with cryogenic CMOS interface electronics.

Voltage references are an essential building block for many electronic systems, such as analog-to-digital and digital-to-analog converters, and voltage regulators. Although state-of-the-art voltage references already demonstrated high performance over the standard temperature range (−40 °C to 125 °C), specific applications require an operating temperature far beyond this range. A relevant example is the electronic interface for quantum processors, for which voltage references that can operate down to cryogenic temperatures are needed. This thesis presents a CMOS-based voltage reference that can work over a wide temperature range from 4K to 300K. To achieve a low-drift, high-accuracy reference, it is designed based on the devices’ cryogenic behaviour to minimize the nonlinearities of the PTAT- (proportional to absolute temperature) and CTAT (complementary to absolute temperature) voltages and combine them to generate a stable output voltage. Dynamic compensation techniques are employed to reduce the effect of process variations and a switched-capacitor circuit is proposed to minimize the output ripple. The targeted specifications of this design are comparable with the state-of-the-art voltage references working at room temperature. To verify the performance at cryogenic temperatures, the design has been taped out in 40nm CMOS technology.

The heart is one of our vital organs. It functions by periodically contracting in a rhythmic way. Sometimes, this rhythmic behaviour is affected by abnormalities in the tissue. These conditions are referred to as cardiac arrhythmias. One kind is of specific interest, called atrial fibrillation (AF). To further study AF, methods have been developed to estimate the conductivity of cardiac cells based on the measured electrical signals. In addition, other parameters of interest besides the conductivity are involved. The goal of this project was to consider one of the parameters in the electrogram (EGM) model: the sensor-to-cell height. First, we studied the effect of the height as a parameter in the model when used for conductivity estimation. To that end, a detector was built with which we can explain the effect of all involved parameters on the ability to accurately estimate any parameters of interest. In addition, we considered the case where the height is unknown and is estimated, thus possibly including estimation errors. The focus was on the consequences of making errors in the estimation of the height with respect to conduction block detection and conductivity estimation. Lastly, the effort was made to estimate the height. Here, the optimisation problem of height estimation was formalised and derived as its implementable form. At first, a simplified EGM model was assumed in order to mimic and estimate cell-specific effects, i.e. the cell conductivities. Then, the height was estimated in various situations to study its behaviour and performance under different conditions. Then, also the standard EGM model was used in the same way, after which we also tested the performance of the designed algorithm in combination with existing conductivity estimation methods.

A key issue in current quantum computing interfaces is the dense interconnect between electronics at cryogenic temperature (CT) and room temperature (RT). Recently, progress has been made to move more control electronics from RT to CT, reducing interconnect overhead. The next step towards minimal interconnect is a direct wireline interface between RT and CT. This work presents a full­rate 10 Gb/s clock­and­data recovery circuit for a high speed serial link receiver operating at CT. A novel phase detector is utilized to reduce power consumption by removing the need for both a pulse generator at the input and, a buffer between the phase detector and voltage controlled oscillator. Additionally, a digital delay­locked loop is added to improve the retiming margin, achieving higher jitter tolerance. Implemented in 40­nm CMOS, post­layout simulation shows a core power consumption of 3.89 mW from a 1.1­V supply at 10 Gb/s, producing an rms­jitter of 84 fs and an estimated jitter tolerance of 1.1 UIpp at 10 MHz.

Due to the precise lithography and highly pure silicon used in IC technology, thermal-diffusivity (TD) temperature sensors can achieve high accuracy without the need for trimming. TD sensors employ electrothermal filters (ETFs) to measure the thermal diffusivity of silicon, i.e. the rate at which heat diffuses through silicon, which is a well-defined function of temperature. This thesis presents two approaches to improve the accuracy and resolution of TD sensors. The first approach investigates the effect of variations in ETF geometry on sensor resolution and proposes a multiplexing scheme to utilize a single readout circuit for reading out multiple ETFs. The second approach aims to investigate the effect of improvements in CMOS technology on sensor accuracy by scaling two ETFs to the 65nm process from the 180nm process. A first-order phase-domain delta-sigma modulator is designed for the readout of the ETFs in the 65nm process, and the previously designed multiplexing scheme is used for cost and time-efficient tape-out. Based on the estimated lithographic error of the 65nm process, the two ETFs are expected to achieve untrimmed inaccuracies of 0.18℃(3𝜎) and 0.36℃(3𝜎), respectively.

In today's highly information-based society, portable smart devices are helping everyone all the time. At the same time, many of them need corresponding power management modules to provide them with stable power from the Li-ion battery. Since different functional modules require different voltage levels, a special DC-DC converter or driver must be designed to meet the requirements. In this thesis, one design is proposed to fulfill the requirement of high efficiency, and another one achieves fully integrated. This thesis proposes a hybrid DC-DC step-up converter with a new architecture by merging a traditional inductor-based (IB) boost converter with a switched-capacitor (SC) converter to boost 3-4.2-V input to 20-30-V output. By serially connecting an IB boost converter and a 1:6 Dickson SC converter, the capacitors take over most of the output voltage stress. As a result, the voltage stress over each switch is limited to 5 V, which makes it possible to implement all the power switches with only on-chip 5-V devices. Thanks to the 5-V devices, the overall power conversion efficiency is improved in various aspects. The switching frequency of the SC stage is decreased by the soft charging technique, which helps further improve the efficiency. The proposed converter is designed and simulated in TSMC 0.18 um BCD process. An efficiency of 93.08 % is achieved under 3.7-V input and 29-V output voltage with a 25-mA current load. A fully integrated VCSEL driver with adjustable pulse width is also proposed in this thesis. By combining two separate control signals, the VCSEL driver is able to overcome challenges posed by PVT and technology process limitations to achieve the narrowest pulse width of around 300-ps. The proposed converter is designed and simulated in SMIC 55 BCD process.