Scaling neural recording systems to thousands of channels creates extreme bandwidth demands, posing a challenge for resource-constrained, implantable devices. This work introduces an adaptive, multi-stage compression framework for high-bandwidth neural interfaces. The system combines a Wired-OR analog-to-digital compressive readout with a digital core that adaptively requantizes, selectively samples, and encodes the neural signals. Although prior work suggests that action potential recordings can be re-quantized to approximately the signal-to-noise (SNR) number of bits without significantly degrading decoding performance, our results show that the required resolution can often be reduced even further. By matching the number of quantization levels to the electrode's maximum SNR ([log ₂SNR] number of bits), we retain waveform fidelity while eliminating unnecessary precision that primarily captures noise. Recorded spike samples are selected using a mutual information-based criterion to preserve both spatial and temporal discriminative waveform features. A static entropy coder completes the pipeline with low computation overhead compression optimized for neural signal statistics. Evaluated on 512-channel macaque retina ex vivo data, the system preserves 90% of spikes while achieving a 1098× total compression over baseline.

This work presents a bidirectional neuromodulation chipset with 64-channel neural analog front-end (AFE), and a four-channel current stimulator. The chipset employs a heterogeneous architecture, combining a 28-nm low-voltage (LV) CMOS process for the AFE and the digital backend (DBE) to improve area and power efficiency, with a 180-nm high-voltage (HV) bipolar-CMOS-DMOS (BCD) process for the stimulation driver to achieve HV compliance. An AFE–DBE co-design framework is proposed to relax AFE noise requirements without sacrificing classification performance in the DBE, thus enabling significant reductions in AFE’s area and power consumption. In addition, we introduce a novel embedded current-steering digital-to-analog converter (IDAC) structure that addresses key limitations of conventional IDACs in multichannel direct-digitization recording architectures, including noise degradation from IDAC switching, and channel-to-channel gain variations. Overall, the proposed chipset achieves HV compliance (10 V) in the stimulator, while maintaining exceptional area and power efficiency in the AFE and DBE. Notably, the AFE achieves the smallest per-channel area (0.0009mm²) and the lowest per-channel power (204nW) reported to date for electrocorticography (ECoG) acquisition (≤1 kHz bandwidth). Together, these results highlight the chipset’s potential for implantable neuromodulation systems that enable long-term monitoring of neurological disorders with closed-loop intervention.

This letter describes a fast-settling active rectifier for a 40.68 MHz wireless power transfer receiver for implantable applications. Fast-settling and low power are achieved through a novel direct voltage-domain compensation technique. The rectifier maintains high efficiency during load and link variations required for downlink communication. The system was fabricated in 40nm CMOS and achieves a voltage conversion ratio of 93.9% and a simulated power conversion efficiency of 90.1% in a 0.19 mm² area, resulting in a 118 mW/mm² power density while integrating the resonance and filter capacitors. The worst-case settling of the ON-and OFF-delay compensation in the active rectifier is 200 ns, which is the fastest reported to date.

A single transmitter source can power multiple ultrasound piezoelectric transducers to enhance the harvested power; however, the received ultrasonic signals vary in phase and amplitude across each element. This paper introduces a fully integrated, high-frequency SSHC rectifier tailored for miniaturized multi-piezo implants to efficiently harvest power at variable phase offsets with a compact form factor. The design incorporates a novel phase-splicing flipping capacitor-sharing technique between all four ultrasound piezoelectric transducers to improve area efficiency. The proposed 4-stage SSHC rectifier can harvest 5.94x more power than a full bridge rectifier operating at a high ultrasonic excitation frequency of 780 kHz. The proposed system was designed using 180-nm BCD process technology for a 2x2 piezoelectric transducer array, with each element featuring an internal capacitor (C_P) of 63.7pF.

This article presents a 1024-channel ultra-low-power spike sorting chip featuring event-driven spike detection and spatial clustering for large-scale neural recording. To address power and scalability constraints in brain–computer interfaces (BCIs), the design integrates a compressive analog-to-digital converter (ADC) with a two-stage spike detector that significantly reduces memory and processing activity. Spatial features derived from high-density micro-electrode array (MEA) enhance cluster separability, enabling robust performance even under neural signal distortion or probe drift, particularly when recordings are obtained using planar MEAs. A modified self-organizing map (SOM) algorithm clusters spikes in the spatial domain with minimal memory access, supporting on-chip training and real-time operation with low latency. Fabricated in 40-nm CMOS, the chip achieves 0.00029-mm²/channel area and 74-nW/channel power consumption, with over 1000× data compression. Performance is validated across synthetic and ex vivo datasets containing up to 500 neurons, demonstrating competitive accuracy and robust drift tracking compared to state-of-the-art solutions with much lower data bandwidth, processing, and power demands.

This paper presents a fully-integrated single-input dual-output power management unit operating both in volt age/current modes for powering mm-scale wireless neural im plants. The chip operates in voltage mode most of the time, using an active full-wave rectifier to regulate a low-voltage, high load output with high power efficiency and low output ripple (<32 mV_pp). It switches to current mode rectification when gen erating a high-voltage, low-load output. This dual-mode operation allows for flexible power distribution and configurable voltage ratios between the two outputs. The selected 40.68 MHz operating frequency reduces the required capacitances for input impedance matching and output filtering, enabling on-chip integration; the only external component is the receiver coil. A novel resonance breakup switch compatible with full-wave rectification ensures a smooth cold start-up of the chip without any external voltage supply. The chip was fabricated using 40-nm CMOS technology with an active area of 1.18 mm² and was tested in a wireless power link. Measurement results demonstrate that the chip can simultaneously regulate two outputs, V_LV = 1 V and V_HV = 2 V, with a tested maximum output power of 10 mW and 32.6 µW on V_LV and V_HV, respectively. At the optimal output power condition (P_LV = 4.4∼6.7 mW), the system achieves a peak power conversion efficiency of 85.87% and a peak end-to-end efficiency of 17.32% when regulating V_LV. The end-to-end efficiency drops by only 2.38% when regulating both outputs with R_LV = 225 Ω and R_HV = 400 kΩ.

Brain-computer interfaces of the future will be recorded from tens of thousands of high-density electrodes. This paper presents a neural amplifier for next-generation single-cell resolution BCIs. The amplifier leverages spatial signal correlation to introduce a novel shared DC servo loop to improve area efficiency while maintaining state-of-the-art power efficiency. Post-layout simulations in 40 nm CMOS technology achieve a 50 dB gain in a [0.1-5.2] kHz bandwidth. The amplifier consumes 920 nW and achieves a total input-referred noise of 8 μ V_rms while occupying only 35 μ m × 35 μ m per recording channel.

This brief presents a low-power oscillatory synchronization feature extraction (FE) unit for phase-amplitude coupling (PAC) and phase locking value (PLV) features. The proposed FE unit uses a new multiplier-less wavelet approximation in combination with a multi-rate lowpass filter bank for low-power complex signal extraction. Further power and area reductions are obtained by utilizing a light sine and cosine extractor (LSCE) for the feature computation. The synthesized 32-channel design achieves state-of-the-art performances in post-layout simulations at 430 nW/channel and 0.36 mm2 while maintaining sufficient accuracy for seizure detection in epileptic patients.

The investigation of neural activity in the murine brain through electrophysiological recordings stands as a fun-damental pursuit within the domain of neuroscience. A specific area of keen interest within this field pertains to the scrutiny of Purkinje cells, nestled within the cerebellum, in order to gain insights into the mechanisms underlying brain injuries and the impairment of motor functions. Notably, Purkinje cells manifest two distinct types of spikes - complex and simple - a pivotal aspect for subsequent classification purposes. However, a critical challenge has persisted in the experimental paradigm: the prevailing setups necessitate the use of wired connections linking the mouse's head stage to data acquisition systems. This constraint substantially curtails the mouse's natural behavior during the course of experimentation, limiting the ability to study essential neural processes and motor function aspects over extended periods. In this paper, we propose a new architectural framework for the detection and classification of neuronal spikes originating from Purkinje cells. This system is engineered to exploit the distinct attributes of these neural entities, effectively winnowing out extraneous data while retaining the pertinent information. The resultant output is a refined dataset, amenable to convenient storage within the mouse's head stage, obviating the need for unwieldy wiring configurations. Our proposed implementation attains a classification accuracy of up to 98% on an in-vivo dataset. Furthermore, its compact form factor en-sures unhindered mobility for the experimental mouse, fostering naturalistic behaviors during the course of scientific inquiry.

Objective. Bi-directional electronic neural interfaces, capable of both electrical recording and stimulation, communicate with the nervous system to permit precise calibration of electrical inputs by capturing the evoked neural responses. However, one significant challenge is that stimulation artifacts often mask the actual neural signals. To address this issue, we introduce a novel approach that employs dynamical control systems to detect and decipher electrically evoked neural activity despite the presence of electrical artifacts. Approach. Our proposed method leverages the unique spatiotemporal patterns of neural activity and electrical artifacts to distinguish and identify individual neural spikes. We designed distinctive dynamical models for both the stimulation artifact and each neuron observed during spontaneous neural activity. We can estimate which neurons were active by analyzing the recorded voltage responses across multiple electrodes post-stimulation. This technique also allows us to exclude signals from electrodes heavily affected by stimulation artifacts, such as the stimulating electrode itself, yet still accurately differentiate between evoked spikes and electrical artifacts. Main results. We applied our method to high-density multi-electrode recordings from the primate retina in an ex vivo setup, using a grid of 512 electrodes. Through repeated electrical stimulations at varying amplitudes, we were able to construct activation curves for each neuron. The curves obtained with our method closely resembled those derived from manual spike sorting. Additionally, the stimulation thresholds we estimated strongly agreed with those determined through manual analysis, demonstrating high reliability ( R 2 = 0.951 for human 1 and R 2 = 0.944 for human 2). Significance. Our method can effectively separate evoked neural spikes from stimulation artifacts by exploiting the distinct spatiotemporal propagation patterns captured by a dense, large-scale multi-electrode array. This technique holds promise for future applications in real-time closed-loop stimulation systems and for managing multi-channel stimulation strategies.

This article presents a data-compressive neural recording IC for single-cell resolution high-bandwidth brain–computer interfaces (BCIs). The IC features wired-OR lossy compression during digitization, thus preventing data deluge and massive data movement. By discarding unwanted baseline samples of the neural signals, the output data rate is reduced by 146× on average while allowing the reconstruction of spike samples. The recording array consists of pulse-position modulation (PPM)-based active digital pixels (ADPs) with a global single-slope (SS) analog-to-digital conversion scheme, which enables a low-power and compact pixel design with significantly simple routing and low array readout energy. Fabricated in a 28-nm CMOS process, the neural recording IC features 1024 channels (i.e., 32 × 32 array) with a pixel pitch of 36 µm that can be directly matched to a high-density micro-electrode array (MEA). The pixel achieves 7.4-µV_rms input-referred noise with a −3-dB bandwidth of 300 Hz–5 kHz while consuming only 268 nW from a single 1-V supply. The IC achieves the smallest area per channel (36 × 36 µm²) and the highest energy efficiency among the state-of-the-art neural recording ICs published to date.

This paper presents a neural recording IC featuring lossy compression during digitization, thus preventing data deluge and enabling a compact active digital pixel design. The wired-OR-based compression discards unwanted baseline samples while allowing the reconstruction of spike samples. The IC features a 32x32 MEA with 36 μ m pixel pitch and consumes 268nW per pixel from a single 1V supply. It achieves 9.8 μ VRMS input-referred noise and 0.3-5kHz bandwidth, resulting in NEF/PEF of 3.7/14.1.

Power and area efficient on-chip feature extraction is needed for future closed-loop neural interfaces. This paper presents a feature extraction unit for neural oscillatory synchrony that bypasses the phase extraction step to reduce hardware complexity. Instead, the sine and cosine of the phase are directly approximated from the real and imaginary components of the signal to calculate the phase-amplitude coupling (PAC) and phase locking value (PLV). The synthesized design achieves state-of-the-art performances at 43 nW/channel and 0.006 mm2, while maintaining sufficient accuracy for seizure detection in epileptic patients.

Future high-density and high channel count neural interfaces that enable simultaneous recording of tens of thousands of neurons will provide a gateway to study, restore and augment neural functions. However, building such technology within the bit-rate limit and power budget of a fully implantable device is challenging. The wired-OR compressive readout architecture addresses the data deluge challenge of a high channel count neural interface using lossy compression at the analog-to-digital interface. In this article, we assess the suitability of wired-OR for several steps that are important for neuroengineering, including spike detection, spike assignment and waveform estimation. For various wiring configurations of wired-OR and assumptions about the quality of the underlying signal, we characterize the trade-off between compression ratio and task-specific signal fidelity metrics. Using data from 18 large-scale microelectrode array recordings in macaque retina ex vivo, we find that for an event SNR of 7-10, wired-OR correctly detects and assigns at least 80% of the spikes with at least 50× compression. The wired-OR approach also robustly encodes action potential waveform information, enabling downstream processing such as cell-type classification. Finally, we show that by applying an LZ77-based lossless compressor (gzip) to the output of the wired-OR architecture, 1000× compression can be achieved over the baseline recordings.