A 1024-Channel 268 nW/pixel 36x36 μm2/ch Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces

Conference paper (2023)

Authors

Moonhyung Jang Stanford University
Moon Hyung Jang Stanford University
Wei-Han Yu University of Macau
Changuk Lee Yonsei University
Maddy Hays Stanford University
Pingyu Wang Stanford University
Nick Vitale Stanford University
Nicholas Vitale Stanford University
Pulkit Tandon Stanford University
Pulkit Tandon Stanford University
Youngcheol Chae Yonsei University
Dante G. Muratore Bio-Electronics - EEMCS
D.G. Muratore Bio-Electronics - EEMCS
More Authors... External organisation
Research Group
Bio-Electronics (EEMCS) (TU Delft)
Copyright: © 2023 Moon Hyung Jang, Wei-Han Yu, Changuk Lee, Maddy Hays, Pingyu Wang, Nick Vitale, Pulkit Tandon, Youngcheol Chae, D.G. Muratore, More Authors
DOI: https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185288
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Published Date

2023

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Bio-Electronics

Abstract

This paper presents a neural recording IC featuring lossy compression during digitization, thus preventing data deluge and enabling a compact active digital pixel design. The wired-OR-based compression discards unwanted baseline samples while allowing the reconstruction of spike samples. The IC features a 32x32 MEA with 36 μ m pixel pitch and consumes 268nW per pixel from a single 1V supply. It achieves 9.8 μ VRMS input-referred noise and 0.3-5kHz bandwidth, resulting in NEF/PEF of 3.7/14.1.

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