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A 1024-Channel 268 nW/pixel 36x36 μm2/ch Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces

Conference Paper (2023)
Author(s)

Moon Hyung Jang (Stanford University)

Wei-Han Yu (University of Macau)

Changuk Lee (Yonsei University)

Maddy Hays (Stanford University)

Pingyu Wang (Stanford University)

Nick Vitale (Stanford University)

Pulkit Tandon (Stanford University)

Youngcheol Chae (Yonsei University)

Dante G. Muratore (TU Delft - Electrical Engineering, Mathematics and Computer Science)

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Research Group
Bio-Electronics
DOI related publication
https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185288 Final published version
More Info
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Publication Year
2023
Language
English
Research Group
Bio-Electronics
Bibliographical Note
Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.
Publisher
IEEE
ISBN (print)
979-8-3503-4669-5
ISBN (electronic)
978-4-86348-806-9
Event
2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 (2023-06-11 - 2023-06-16), Kyoto, Japan
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Abstract

This paper presents a neural recording IC featuring lossy compression during digitization, thus preventing data deluge and enabling a compact active digital pixel design. The wired-OR-based compression discards unwanted baseline samples while allowing the reconstruction of spike samples. The IC features a 32x32 MEA with 36 μ m pixel pitch and consumes 268nW per pixel from a single 1V supply. It achieves 9.8 μ VRMS input-referred noise and 0.3-5kHz bandwidth, resulting in NEF/PEF of 3.7/14.1.

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