This article presents a 1024-channel ultra-low-power spike sorting chip featuring event-driven spike detection and spatial clustering for large-scale neural recording. To address power and scalability constraints in brain–computer interfaces (BCIs), the design integrates a compressive analog-to-digital converter (ADC) with a two-stage spike detector that significantly reduces memory and processing activity. Spatial features derived from high-density micro-electrode array (MEA) enhance cluster separability, enabling robust performance even under neural signal distortion or probe drift, particularly when recordings are obtained using planar MEAs. A modified self-organizing map (SOM) algorithm clusters spikes in the spatial domain with minimal memory access, supporting on-chip training and real-time operation with low latency. Fabricated in 40-nm CMOS, the chip achieves 0.00029-mm²/channel area and 74-nW/channel power consumption, with over 1000× data compression. Performance is validated across synthetic and ex vivo datasets containing up to 500 neurons, demonstrating competitive accuracy and robust drift tracking compared to state-of-the-art solutions with much lower data bandwidth, processing, and power demands. ... Read more

Next-generation brain-computer interfaces will enable motor and speech decoding in humans [1]-[3] and improve our understanding of brain function [4]. To achieve this requires high-density multi-electrode arrays (HD-MEA) [5], [6]. This leads to massive amounts of raw data that must be reduced on-chip to enable wireless operation [7]. Spike sorting (SS) assigns spikes to putative neurons and can reduce the data rate substantially because only the neuron ID needs to be transmitted when a spike occurs. Prior art focuses on improving the scalability and power efficiency of on-chip SS [8]-[15]. However, they either require a large input buffer [12]-[14], use temporal features (TF) that do not scale well to multi-channel systems [8]-[13], access the entire clustering memory for every spike [11]-[13], or use high power [8]-[11] and area [8]-[10]. This work uses event-driven spike detection and spatial spike sorting to deal with these challenges and achieve 74nW/ch, 0.00029mm2/ch, and <50μs latency with 1024 channels. This represents a >10x improvement in power and area efficiency with 3x more channels than prior art (Fig. 15.2.6). ... Read more