This article presents a 1024-channel ultra-low-power spike sorting chip featuring event-driven spike detection and spatial clustering for large-scale neural recording. To address power and scalability constraints in brain–computer interfaces (BCIs), the design integrates a compressive analog-to-digital converter (ADC) with a two-stage spike detector that significantly reduces memory and processing activity. Spatial features derived from high-density micro-electrode array (MEA) enhance cluster separability, enabling robust performance even under neural signal distortion or probe drift, particularly when recordings are obtained using planar MEAs. A modified self-organizing map (SOM) algorithm clusters spikes in the spatial domain with minimal memory access, supporting on-chip training and real-time operation with low latency. Fabricated in 40-nm CMOS, the chip achieves 0.00029-mm²/channel area and 74-nW/channel power consumption, with over 1000× data compression. Performance is validated across synthetic and ex vivo datasets containing up to 500 neurons, demonstrating competitive accuracy and robust drift tracking compared to state-of-the-art solutions with much lower data bandwidth, processing, and power demands.

This brief presents a low-power oscillatory synchronization feature extraction (FE) unit for phase-amplitude coupling (PAC) and phase locking value (PLV) features. The proposed FE unit uses a new multiplier-less wavelet approximation in combination with a multi-rate lowpass filter bank for low-power complex signal extraction. Further power and area reductions are obtained by utilizing a light sine and cosine extractor (LSCE) for the feature computation. The synthesized 32-channel design achieves state-of-the-art performances in post-layout simulations at 430 nW/channel and 0.36 mm2 while maintaining sufficient accuracy for seizure detection in epileptic patients.

Future high-density and high channel count neural interfaces that enable simultaneous recording of tens of thousands of neurons will provide a gateway to study, restore and augment neural functions. However, building such technology within the bit-rate limit and power budget of a fully implantable device is challenging. The wired-OR compressive readout architecture addresses the data deluge challenge of a high channel count neural interface using lossy compression at the analog-to-digital interface. In this article, we assess the suitability of wired-OR for several steps that are important for neuroengineering, including spike detection, spike assignment and waveform estimation. For various wiring configurations of wired-OR and assumptions about the quality of the underlying signal, we characterize the trade-off between compression ratio and task-specific signal fidelity metrics. Using data from 18 large-scale microelectrode array recordings in macaque retina ex vivo, we find that for an event SNR of 7-10, wired-OR correctly detects and assigns at least 80% of the spikes with at least 50× compression. The wired-OR approach also robustly encodes action potential waveform information, enabling downstream processing such as cell-type classification. Finally, we show that by applying an LZ77-based lossless compressor (gzip) to the output of the wired-OR architecture, 1000× compression can be achieved over the baseline recordings.

Power and area efficient on-chip feature extraction is needed for future closed-loop neural interfaces. This paper presents a feature extraction unit for neural oscillatory synchrony that bypasses the phase extraction step to reduce hardware complexity. Instead, the sine and cosine of the phase are directly approximated from the real and imaginary components of the signal to calculate the phase-amplitude coupling (PAC) and phase locking value (PLV). The synthesized design achieves state-of-the-art performances at 43 nW/channel and 0.006 mm2, while maintaining sufficient accuracy for seizure detection in epileptic patients.