This work presents a bidirectional neuromodulation chipset with 64-channel neural analog front-end (AFE), and a four-channel current stimulator. The chipset employs a heterogeneous architecture, combining a 28-nm low-voltage (LV) CMOS process for the AFE and the digital backend (DBE) to improve area and power efficiency, with a 180-nm high-voltage (HV) bipolar-CMOS-DMOS (BCD) process for the stimulation driver to achieve HV compliance. An AFE–DBE co-design framework is proposed to relax AFE noise requirements without sacrificing classification performance in the DBE, thus enabling significant reductions in AFE’s area and power consumption. In addition, we introduce a novel embedded current-steering digital-to-analog converter (IDAC) structure that addresses key limitations of conventional IDACs in multichannel direct-digitization recording architectures, including noise degradation from IDAC switching, and channel-to-channel gain variations. Overall, the proposed chipset achieves HV compliance (10 V) in the stimulator, while maintaining exceptional area and power efficiency in the AFE and DBE. Notably, the AFE achieves the smallest per-channel area (0.0009mm²) and the lowest per-channel power (204nW) reported to date for electrocorticography (ECoG) acquisition (≤1 kHz bandwidth). Together, these results highlight the chipset’s potential for implantable neuromodulation systems that enable long-term monitoring of neurological disorders with closed-loop intervention.

This brief presents a low-power oscillatory synchronization feature extraction (FE) unit for phase-amplitude coupling (PAC) and phase locking value (PLV) features. The proposed FE unit uses a new multiplier-less wavelet approximation in combination with a multi-rate lowpass filter bank for low-power complex signal extraction. Further power and area reductions are obtained by utilizing a light sine and cosine extractor (LSCE) for the feature computation. The synthesized 32-channel design achieves state-of-the-art performances in post-layout simulations at 430 nW/channel and 0.36 mm2 while maintaining sufficient accuracy for seizure detection in epileptic patients.

Power and area efficient on-chip feature extraction is needed for future closed-loop neural interfaces. This paper presents a feature extraction unit for neural oscillatory synchrony that bypasses the phase extraction step to reduce hardware complexity. Instead, the sine and cosine of the phase are directly approximated from the real and imaginary components of the signal to calculate the phase-amplitude coupling (PAC) and phase locking value (PLV). The synthesized design achieves state-of-the-art performances at 43 nW/channel and 0.006 mm2, while maintaining sufficient accuracy for seizure detection in epileptic patients.