This work presents a bidirectional neuromodulation chipset with 64-channel neural analog front-end (AFE), and a four-channel current stimulator. The chipset employs a heterogeneous architecture, combining a 28-nm low-voltage (LV) CMOS process for the AFE and the digital backend (DBE) to improve area and power efficiency, with a 180-nm high-voltage (HV) bipolar-CMOS-DMOS (BCD) process for the stimulation driver to achieve HV compliance. An AFE–DBE co-design framework is proposed to relax AFE noise requirements without sacrificing classification performance in the DBE, thus enabling significant reductions in AFE’s area and power consumption. In addition, we introduce a novel embedded current-steering digital-to-analog converter (IDAC) structure that addresses key limitations of conventional IDACs in multichannel direct-digitization recording architectures, including noise degradation from IDAC switching, and channel-to-channel gain variations. Overall, the proposed chipset achieves HV compliance (10 V) in the stimulator, while maintaining exceptional area and power efficiency in the AFE and DBE. Notably, the AFE achieves the smallest per-channel area (0.0009mm²) and the lowest per-channel power (204nW) reported to date for electrocorticography (ECoG) acquisition (≤1 kHz bandwidth). Together, these results highlight the chipset’s potential for implantable neuromodulation systems that enable long-term monitoring of neurological disorders with closed-loop intervention.

High-resolution, large-scale neural recording from the cortical surface, using passive micro-electrocorticography (µECoG) arrays paired with CMOS readout integrated circuits (ROICs), is fundamentally limited by interconnect bottlenecks. Emerging active multiplexing mitigates this; yet existing solutions often exhibit limitations in bandwidth and channel count. Furthermore, current DC-coupled recording analog front-ends (AFEs) suffer from degraded noise performance in the presence of large electrode DC offsets (EDOs). To address these challenges, this article presents a compact, low-power neural ROIC tailored for the acquisition of both low-frequency ECoG signals and wide-band cortical-surface action potentials (APs) from high-density active µECoG arrays. Employing 32:1 time-division multiplexing, our ROIC supports simultaneous recording from 3072 electrodes using 96 time-multiplexed channels (super-channels). To achieve high area and power efficiencies, each super-channel features two-step incremental-successive approximation register (I-SAR) conversion and embedded bulk-DACs (BDACs) for efficient EDO and comparator offset compensation. Fabricated in a 22-nm fully depleted silicon on insulator (FDSOI) process, this prototype neural ROIC achieves the highest channel count, the smallest effective per-channel area (0.0004 mm²), and the lowest per-channel power (438 nW), while maintaining a low input-referred noise (IRN) of 2.39  µV_rms and 5.91 µV_rms in the ECoG (1–300 Hz) and AP (0.3–7.5 kHz) bands, respectively. The ROIC’s ability to record multiplexed neural spikes has experimentally been demonstrated in saline.