This thesis will discuss the design, simulations and measurements of a powerline communication system that utilizes FSK modulation in order to transfer information from a transmitter to a receiver at a baud rate of 1kbps, in order to reach the requirement of having an effective data rate of at least 6bps. This system is designed specifically to be implemented in the smart DC grid of a sustainable "tiny house" community. This thesis investigates the different subsystems needed to create this communication system and compares different methods and implementations. This research led to the conclusion that the communication system was successfully build and could reliably reach a baud rate of 700bps, which appeared to be more than enough to reach a data rate of 6bps. The system also showed to be resistant to 'high levels' of noise on the communication channel as defined in the CELENEC standard. Furthermore, in order to decrease the bit error rate further, additional bit error detection and correction has been implemented using microcontrollers. This led to a robust and nearly error free communication system over a tested powerline of 50 meters long.

Switched-capacitor power converters (SCPCs) have emerged as promising alternatives to traditional inductive power converters due to their CMOS integration capability and configurable conversion ratios. However, challenges such as output ripple, power efficiency, and transient response have hindered their widespread adoption. This article presents a novel Hybrid Hysteresis-CFM (HHC) control strategy that effectively addresses these issues. The HHC strategy combines the best of both worlds, integrating hysteresis control and Continuous Frequency Modulation (CFM) control. During transient moments, the system utilizes a coarse/fine frequency tuning approach to rapidly reach the target frequency. Simultaneously, hysteresis control ensures that overshoot and undershoot are kept within predefined limits, significantly reducing output ripple during load transitions. To enhance performance and versatility, the proposed system employs a Recursive Switched Capacitor (RSC) topology with adaptive capacitor sizing and 10-phase time-interleaving. This configuration enables configurable voltage-conversion ratios (VCRs) and high power conversion efficiency (PCE) across a wide input-output range. Experimental results validate the effectiveness of the HHC SCPC. It demonstrates minimal overshoot and undershoot during load transition, maintains a low output voltage ripple during steady-state operation, and achieves high PCE. Comparative analysis with state-of-the-art DC-DC converters underscores the superior performance of the proposed system. In summary, the Hybrid Hysteresis-CFM (HHC) control strategy offers a promising solution to enhance the capabilities of switched-capacitor power converters. Its ability to address output ripple, power efficiency, and transient response challenges makes it a valuable innovation for diverse applications requiring efficient power conversion.

Traditional power batteries have been unable to meet the requirements of wireless sensor network (WSN) applications which require battery lifetime and no battery replacement. So, harvesting ambient energy and converting it into electrical energy to power wireless sensors has become an alternative to the traditional power sources. Harvesting energy from heat using thermoelectric generators (TEG) has become a prevalent topic in recent years. Since the system is required to startup with zero energy stored, the cold startup technique is necessary to activate the operation of the system in the very beginning stage without any assistance from the energy storage block, for instance, battery and capacitor. It is noted that any machines that moves, shakes, or rotates not only dissipate heat while working but also vibrate, thus the mechanical vibration can be used to startup the system. In this thesis project, a novel piezoelectric generator (PEG) startup technique is proposed to activate the system. This project focuses on pushing the minimum startup TEG voltage to an ultra-low level with the help of the PEG startup circuit. The design of the system follows the top-down approach. Firstly, the inductive DC/DC boost converter was chosen to be the basic topology. Then, the Maximum Power Point Tracking (MPPT) technique is exploited to make sure the TEG always works at its optimal state. In addition, a Zero-current Switching (ZCS) block is proposed to regulate the synchronization of the switches and control the gate switching. Next, the state detector block monitors the state of the harvester system and instructs other control circuits to respond to the changes in the operation state. To avoid the impact of the fluctuation of supply on powering internal control circuits, a low-dropout regulator (LDO) is adopted to generate a stable supply instead. Finally, the power losses, conversion efficiency and startup principle are analyzed and calculated for performance improvement.

In today's highly information-based society, portable smart devices are helping everyone all the time. At the same time, many of them need corresponding power management modules to provide them with stable power from the Li-ion battery. Since different functional modules require different voltage levels, a special DC-DC converter or driver must be designed to meet the requirements. In this thesis, one design is proposed to fulfill the requirement of high efficiency, and another one achieves fully integrated. This thesis proposes a hybrid DC-DC step-up converter with a new architecture by merging a traditional inductor-based (IB) boost converter with a switched-capacitor (SC) converter to boost 3-4.2-V input to 20-30-V output. By serially connecting an IB boost converter and a 1:6 Dickson SC converter, the capacitors take over most of the output voltage stress. As a result, the voltage stress over each switch is limited to 5 V, which makes it possible to implement all the power switches with only on-chip 5-V devices. Thanks to the 5-V devices, the overall power conversion efficiency is improved in various aspects. The switching frequency of the SC stage is decreased by the soft charging technique, which helps further improve the efficiency. The proposed converter is designed and simulated in TSMC 0.18 um BCD process. An efficiency of 93.08 % is achieved under 3.7-V input and 29-V output voltage with a 25-mA current load. A fully integrated VCSEL driver with adjustable pulse width is also proposed in this thesis. By combining two separate control signals, the VCSEL driver is able to overcome challenges posed by PVT and technology process limitations to achieve the narrowest pulse width of around 300-ps. The proposed converter is designed and simulated in SMIC 55 BCD process.

This work proposes an energy harvesting platform that is able to convert power from both DC sources (photo-voltaic cells and TEGs) as well as piezo element sources. It does so only using a single input channel to which a single harvester can be connected. The proposed system is able to differentiate between the two source types and adjust the power converter configuration accordingly.For the DC sources, a novel switched-capacitor power converter (SCPC) is proposed, that is able to convert the energy from a harvester that has a maximum power point (MPP) output voltage of 170mV to 5V and a maximum power point output power of 10uW to 50mW. This DC-DC converter offers 119 different positive voltage conversion ratios, with a maximum voltage conversion ratio of 16, using four in-package capacitors. As a result of this high number of conversion ratios, the MPP output voltage of the harvester and the input voltage of the power converter are matched accurately, causing the harvesting efficiency to be very high. A maximum harvesting efficiency of 96.2% is found in simulations. For the piezo element sources, the concept of a flipping-capacitor rectifier (FCR) has been adjusted to work in harmony with the designed SCPC. In a steady-state condition, the capacitors of the SCPC reach specific voltages, such that they can create evenly spaced voltage steps for the flipping operation. With this technique, a voltage flipping efficiency of 0.9375 and a theoretical maximum output power improvement rate (MOPIR) of 32 can be reached. Due to losses in the system, simulation results show a MOPIR of up to 20.0, which is still significantly higher than the state-of-art. The system is designed to work with harvesters with a piezo capacitance of up to 100nF, an excitation frequency of 1Hz to 200Hz and an equivalent FBR maximum power point output power of 1uW to 50mW. An implementation of the proposed system is discussed and simulated. The total active silicon area for the designed system is 2.12mm2 in a 0.18 um TSMC technology.

Multiple voltage conversion ratio (VCR) recursive switched-capacitor (SC) DC-DC converters, based on a number of basic 2:1 converters, are widely used for on-chip power supplies due to their flexible VCRs for higher energy efficiency. However, conventional multi-VCR SC converters usually have one or more 2:1 converters unused for some VCRs, which results in lower power density and chip area wastage. This paper presents a new recursive DC-DC converter system, which is able to dynamically reconfigure the connection of all on-chip 2:1 converter cells so that the unused converters in conventional designs can be re-used in this new architecture for increasing the load-driving capacity, power density and power efficiency. To validate the design, a 4-bit-input 15-ratio system was designed and fabricated in a 180-nm BCD process, which can support a maximum load current of 0.71mA and achieve a peak power efficiency of 93.1% with 105.3μA/mm^2 chip power density from a 2V input power supply. The measurement results show that the load-driving capacity can become 6.826×, 2.236× and 2.175× larger than the conventional topology when the VCR is 1/2, 1/4 and 3/4, respectively. In addition, the power efficiency under these specific VCRs can also be improved considerably.

Bidirectional neural recording ICs faces the challenge of simultaneous stimulation and recording. The recording IC should endure large stimulation artifacts while capturing weak neural signals excited by the stimuli. The stimulation artifacts can be as large as hundreds of millivolts, which can saturate the recording front end. Conventional neural-recording ICs use a low-noise-amplifier (LNA), a programmable-gain amplifier (PGA) followed by an analog-to-digital converter (ADC), leading to low power consumptions and great noise performances. However, the dynamic range (DR) is usually limited to 50 dB. State-of-the-art recording ICs using direct-conversion ADCs have been intro- duced to increase the DR. However, the typical power and area consumption for these architectures are exceeding the requirements for next-generation brain-computer interfaces. This work proposes a novel neural-recording IC system architecture with satu- ration prevention in presence of large stimulation artifacts. The proposed architecture consists of an AC-coupled boxcar sampler, switched-capacitor low-pass filter followed by a 10-bit asynchronous SAR ADC. The integrated voltage at the output of the boxcar sampler is sampled by the ADC and monitored by a level-cross detection block. Based on the output of the level-cross detection block, the integration time, and thus the gain, can be tuned to different configurations pre-defined in a look-up table (LUT). The additional noise penalty due to noise-folding from decreasing the integration time is compensated by oversampling and averaging. The proposed system architecture is partially imple- mented at transistor level while the ADC and digital blocks are modeled using verilog-A as a proof-of-concept. The analog front-end achieves a DR of 69.5 dB with a peak-to-peak maximum input amplitude of 180 mVPP and a typical ENOB of 8.01 bits.

With the high-speed development of the Internet of Things (IoT), powering such a massive number of wireless IoT sensors with chemical batteries become more and more unpractical. To make the IoT sensors self-sustained, Piezoelectric Energy Harvesting (PEH) technology provides an excellent solution to power the devices with a relatively long service time. By harvesting the ambient mechanical vibrations, PEH could generate a stable power source without wind or light. Currently, the famous bearing manufacturer, SKF, collaborates with TU Delft to design a self-sustained smart IoT roller with PEH technology, which will be implanted in huge bearings, such as the bearing in the wind turbines. This thesis project is a feasibility study investigating the possibility of replacing the chemical battery with the Piezoelectric Energy Harvester in SKF's smart IoT roller, called Sensor Roller. The objective of this project includes the system design of two generations of the prototype harvester. The first prototype concentrates on the properties of the piezoelectric material, while the second prototype focuses on the structure of the harvester. The design work consists of the raw data analysis of the target roller from SKF and the prototype construction and simulation in COMSOL Multiphysics. Besides, to make the results more reliable, two stages of the test with the practical components are made to study the harvester's performance under the actual working condition of the roller in the bearing. As a result, a tube shape Piezoelectric Energy Harvester with suitable materials and parameters is built. According to the simulation results, under a safe pressure level of the piezoelectric material, the proposed harvester achieves 8.1mW output power, which is enough for the loading sensors. The designed Piezoelectric Energy Harvester is being manufactured at present, and it is planned to be installed in the target roller to get the system-level test in the future. In addition to the harvester, some rectifiers are designed and taped out to improve the performance of the proposed Piezoelectric Energy Harvesting system. Three rectifiers are made with the Silicon Carbide (SiC) process to obtain a high voltage and temperature tolerance: a Full Bridge Rectifier (FBR), a Passive Rectifier, and a Synchronized Switch Harvesting on Inductor (SSHI) rectifier. Meanwhile, another SSHI rectifier is made with the 0.18um Silicon BCD process that focuses on solving the cold-startup problem. Consequently, simulated with the real transducer of the proposed harvester, both the FBR circuit and the Passive Rectifier circuit with the SiC process achieve over 10mW output power, and the SiC SSHI circuit achieves 37.1mW output power. As for the cold-startup SSHI rectifier circuit, it successfully reduces the required open circuit voltage by 4x to start up the SSHI system from the cold state. The results of this project show the great potential for applying the Piezoelectric Energy Harvesting technology to power the IoT sensors in the roller of bearing. Although some future works should be finished to build the commercial version of the energy harvesting roller, we are convinced that the fully self-sustained Sensor Roller with Piezoelectric Energy Harvesting technology will possibly show up in the near future.

This work proposes an energy harvesting DC-DC converter that is able to efficiently process a wide input power range from 25 mW up to 250 mW, to charge a storage device used in Internet-of-Things (IoT) applications. An interleaved boost-converter topology with two inductors is used to divide the high currents over the two branches, in order to reduce the conduction losses in the MOSFET power switches at high input power. A Maximum Power Point Tracking (MPPT) strategy is employed to find the optimal matching between the harvesting sensor, which in this case is a solar cell, and the input of the converter. The Maximum Power Point (MPP) is found by measuring the output current of the converter, decreasing the duty cycle of the switching power MOSFETs, and again measuring the output current to check if it increases. This process is repeated until the output current no longer increases, which is where the MPP will be. The duty-cycle pulses that control the power switches are generated by comparing a reference voltage representing the duty cycle with two sawtooth waves with a phase difference of 180 degrees generated on-chip. Usually, for converters that handle large currents, large power switches are required to keep the on-resistance of the switches minimal such that the conduction losses do not dominate. Since the converter also needs to be able to efficiently convert smaller powers, the size of the power switches is made configurable. This is necessary since otherwise the gate-charge losses will become dominant. The total size of the segmented power switches are controlled digitally by a logic unit that calculates the expected input current using 2-bit representations of the measured output current and the two most significant bits of the 5-bit representation for the duty cycle set by the MPPT. Schematic simulation results show a conversion efficiency of up to 92%. The proposed system is designed and simulated using 180 nm TSMC CMOS technology. The chip covers a total silicon area of 2.20 mm2, with an active area of 1.12 mm2.

This article presents a novel wide operational range reconfigurable regulating rectifier for wireless power transfer. The proposed 1X/2X/3X rectifier achieves wide range voltage regulation without global loop control to minimize the area occupation. Compared with previous work, more working modes and greater magnification allow the proposed rectifier to regulate smaller signal, which extends voltage regulation range. A novel local loop control system is proposed for voltage rectification with three modes. The local loop adaptively senses the duty cycle of mode signal to determine which two working modes the rectifier should work with and configure the rectifier in these two modes. Then the rectifier are switching between two working modes according to the comparison result with reference voltage. Also, the change of which two working modes are also triggered by a window comparator to make sure the change happens when the output voltage is far away from reference voltage. The system is designed and simulated in a 0.18um BCD technology. The measurement results show that the proposed system can rectify wide-range input AC power to a regulated output. The achieved voltage conversion ratio (VCR) is 0.95-2.68 with a peak power conversion efficiency (PCE) of 87.4%.

Depth sensing technology has developed rapidly recently due to its broad applications. Time-of-Flight (ToF) is a popular technology in depth sensing because of its advantages in high measuring accuracy and low complexity in image processing. ToF technologies are divided into two kinds: indirect time-of-flight (iToF) and direct Time-of-Flight (dToF). Compared to the iToF, dToF can detect targets at a longer distance by directly calculating the flight time of the laser. To obtain time information, the dToF system requires a Time-to-Digital Converter (TDC). This thesis proposes a system-level model to optimize the TDC parameters for a dToF system used in an autofocus system of a mobile phone. According to the simulation result of the system modeling, a ring-based TDC is chosen and built using a shared and duty-cycled Voltage-Controlled Oscillator (VCO). To decrease the DNL of the TDC, chopping comparators are used in this design. In addition, to save power and area, a new method called double sampling is used to align the coarse and fine phases of the ring based TDC. The proposed TDC achieves a resolution of 100 ps and a DNL of −0.27/+0.37 and an average power of 0.179 mW/TDC, which are smaller than that of state-of-the-art TDCs used in dToF systems. SMIC 55BSC technology is used to design and tape out the TDC.

The number of IoT devices and their applications is projected to continue increasing in the future, creating a demand for low-power wireless communications that allow IoT devices to either be connected directly to the internet or to use other devices as a back gate to it. BLE is already one of the most used wireless communication protocols for this kind of devices, and its use is expected to continue increasing in the near future. Therefore the need for very low-power Bluetooth baseband designs arises. This thesis work presents a study on previous existing BLE baseband architectures. It proposes a new BLE baseband architecture where every non-bit-intensive function has been moved into software to fully make use of the efficient processor core in the SoC, and new functionalities have been added to the design in order to eliminate unnecessary communication between the baseband and processor. Furthermore, a novel non table based CRC error correction algorithm has been implemented in hardware and included in the bitstream processing chain in order to improve the reliability of the connection and therefore further reduce power consumption. In order to test the functionality of the proposed architecture, the bitstream processing blocks have been implemented and connected to a RISC-V processor core on the designed SoC. That was possible thanks to Chisel, a novel HDL based on Scala, and the Rocket-Chip generator that facilitates the task of integrating parameterizable cores and accelerators/coprocessors into an SoC design. The presented design has been simulated and implemented on a FPGA to test it and show its feasibility.

This thesis presents a 48V-to-1V 10-level dual inductor hybrid converter (DIHC) containing 11 on-chip switches and an off-chip Gallium Nitride (GaN) switch. Thanks to the 10-level Dickson switched-capacitor (SC) circuit, most of the voltage stress will be taken over by off-chip capacitors, which reduces the voltage stress of each switch to 4.8 V and takes full advantage of the voltage pressure on the 5-V on-chip transistors. This proposed structure is implemented in a 0.18-μm BCD process to convert 48-V input to 1-V output with up to 18-A current load. The post-layout simulations show that a peak power efficiency of 90.6% can be achieved at 5.2-A loading and the power density is about 2093 W/in3 considering the power stage volume. This thesis also proposes a 48V/3V multi-resonant DC-DC converter for data center applications, consisting of a 3Φ-SC stage and a 4-to-1 series-parallel stage. Thanks to the multi-phase resonant operation mode, the converter uses fewer components to achieve the same voltage conversion ratio as the conventional two-phase SC converters, and can further improve the efficiency by realising soft-charging. This topology is simulated in cadence spectre, and achieves a peak efficiency of 96.94%, and 95.0% full load efficiency at 30-A load.

The current generation of power management integrated circuits require fully integrated, low cost and low power solutions for voltage regulation. As final blocks in the internal power supply chain, excellent performance linear voltage regulators are required, especially in terms of dynamic response and stability. Since many voltage regulators are used, the chip area consumed by the regulators is a point of attention. Additionally, for some internal voltages the load current or capacitive loading is much lower, such that a scalable compact solution would be preferred. This project focuses on minimizing the on-chip area of voltage regulators while maximizing their performance. The proposed design incorporates a novel circuit technique for improving the dynamic response of linear voltage regulators. In this thesis, the theory and analysis of current amplifier-based NMOST linear voltage regulators is introduced. In order to maximize the dynamic performance, multiple implementations are analyzed and their drawbacks are presented. Adaptive biasing has been implemented in order to improve the slew rate at the gate of the pass transistor and to increase the voltage loop gain bandwidth. The current loop is stabilized by means of bandwidth enhancement resistors, reaching a unity gain frequency of over 500MHz at maximum load current condition. The linear voltage regulator occupies an area of 0.0078 mm2, consumes a quiescent current of 8.5µA and has a current capability of 10 mA. The circuit operates at supply levels varying between 7 to 18V, provides an output regulated voltage of 1.8V and is scalable in terms of the load capacitance and the load current. This design achieves a FOM of 0.613ps and is comparable to state-of-the-art designs.

The development of the Internet of Things has given rise to enormous new industries and applications, including automobiles, smart healthcare systems, smart houses, etc, and the power supply has become the major constraint preventing them from further increasing logic speed. Thus, a SC(switch-capacitance) DC-DC converter with high efficiency, integration on-chip, and multiple voltage conversion ratio (VCRs) is significantly important.SAR(successive Approximation Register) SC was published in 2013, it realized 2n − 1 voltage conversion ratios with n 2:1 SC stage with the cost of charge sharing loss. In 2014, Recursive topology minimized charge-sharing loss by maximizing the connection to the power rail to improve efficiency. While both topologies only offer 7 VCRs for 3 stages, the new topology utilizing the voltage negative feedback technique has expanded this range to 79 ratios, including all p/q rational ratios from 1/2 to 15/16.Each ratio is written in the form Vout=A ∗ VDD − B ∗ Vout, and only three voltage negative feedback module(negators) are to be used :VDD −Vout,2VDD −Vout,−Vout.This paper presents an improved design to expand this VCR range to boost operation, achieving VCR from 15/16 to 16 times the input. In total,3 2:1 SC stages and 3 negators are applied, with a total capacitance of 1.3nF. The capacitance of 3 stages and negators are 130p,260p,520p, and 130p respectively. The system was designed and fabricated in a 180-nm BCD process, the peak efficiency is achieved at a 2:1 ratio @20MHz, with an efficiency of 82.28%, reached load current =6.4mA. The layout area is approximately 2.084mm2 , and the current density estimated is 3.07 mW/mm2. The design has remarkably expanded the 79 VCR options to both buck operation and boost operation

Time-of-Flight (ToF) is an optical range detection technique that derives range from the round-trip time of light pulse between the imager and the target. Due to the simple hardware and distance extraction algorithm, ToF imagers are widely adopted in existing (automotive, consumer electronics, etc.) and emerging (AR/VR, etc.) applications requiring depth information. ToF is divided into Direct-ToF (D-ToF) and Indirect-ToF (I-ToF). Compared with the D-ToF system which directly measures the round-trip time of the laser beam, the I-ToF system indirectly measures the time from a phase measurement of the received modulated pulse. I-ToF provides a smaller detection range but it is less sensitive to jitter in the system and can achieve higher accuracy. Hence, I-ToF is used in short-range high precision applications such as face recognition. This thesis describes the readout ADC design for the next-generation I-ToF imagers used for smartphone face recognition in collaboration with Infineon. A compact 11-bit 2 MS/s column-level ADC is developed in 65nm CMOS image technology. To balance between the available area and required speed, a hybrid SAR-RAMP ADC concept is proposed, which also embeds a threshold comparison phase to relax requirements on successive phases. The ADC has been verified with the post-layout extracted view of the column-level analog circuits and the schematic view of the central/digital circuits with an ideal ramp buffer, achieving a 1.1 V - 3.3 V input range with a 1.1 V reference, a signal-to-noise and distortion ratio (SNDR) of 64.3 dB, 45 µW power consumption, a Walden figure of merit (FOM$_W$) of 107 fJ/conv-step and an area of 7 µm $ imes$ 815 µm.

The growing demand for asynchronous data communication leads to a growing demand for CDR systems to recover the sampling clock of the received data. The DTC in the CDR system is the main jitter source of the recovered data. A low-jitter DTC is required to generate data of low-jitter performance, calling for the application of a phase noise filter. Currently, most phase noise filters are based on the charge injection technique, which can only filter the phase noise of the DLL-based DTC. This thesis presents a new phase noise filter, which can filter both the DLL and PI phase noise. The proposed phase noise filter is inspired by the noise transfer function from the phase detector’s input to the delay locked loop(DLL) output of a type-II DLL, which shows a first-order low-pass transfer function. The noise suppression pole frequency is adjustable and can be modified by changing the gain of each component in the circuit. In addition, by carefully placing the frequency of the LDO’s pole, second-order noise filtering can be realized. During design, a 10-bit DTC is constructed first and the proposed filter is placed behind the DTC to verify the effectiveness of the filter. The design achieves the post-layout level. The simulation results show that the DTC’s phase noise drops from 1.099 psrms to 315.9 fsrms with the filter. The area is 695 μm × 693.5 μm. The design consumes 42.3 mW with 1.8V supply in 180nm BCD technology.