This paper proposes an on-chip sigma regulation system for the accurate and power-efficient control of piezoelectric resonator (PR)-based DC-DC converters to address the challenges of conventional off-chip controllers. A zero-standby sigma-mode is implemented for transient response/output power improvement. Peak efficiencies of 91.2% and 90.7% are achieved for the PR converter and the PR-sigma converter respectively.

With the rapid development of the Internet of Things (IoT), piezoelectric energy harvesting has emerged as a highly promising power solution for autonomous IoT devices. To increase the extracted energy from the harvesters, various rectifiers have been developed. Bias-flip rectifiers, one of the most widely used rectifiers, utilize extra components to periodically flip the voltage across the harvester to achieve higher output power. This work proposes a bias-flip rectifier with an energy investment technique to boost the total harvesting power. By optimizing the energy invested from the load to the harvester and the loading conditions, the circuit can achieve higher FoM compared to conventional SSHI rectifiers under the same configurations. The proposed circuit was designed in a 180-nm BCD process, the simulation results show a 5.97 X energy enhancement compared to a full bridge rectifier (FBR) and a 1.2 X enhancement compared to conventional synchronized switch harvesting on inductor (SSHI) rectifiers.

Multiply-accumulators are key cornerstone arithmetic blocks for AI accelerators to achieve high energy efficiency, high accuracy and small silicon area, especially for edge accelerators (Fig. 1, left). The trend of edge accelerators is to use Analog and Mixed-Signal (AMS) domain circuits to improve energy efficiency by reducing voltage swing and integrating more operations into one computation unit [16]. Fig. 1 (right) shows the major issues in existing capacitor-based AMS domain Multiply-ACcumulator (MAC) designs: 1) High energy consumption brought by the high-switching-activity digital logic gates and high-voltage-swing charge-domain analog adders [3, 4]; 2) Significant accuracy loss due to the poor linearity from capacitor parasitic and device mismatch [3]; 3) Large area overhead caused by the parallel unit-capacitors in summation [4, 5].