The growing trend of the Internet of Things (IoT) involves trillions of sensors in various applications. An extensive array of parameters need to be gathered concurrently with high-precision, low-cost, and low-power sensor nodes, such as resistive (R) and capacitive (C) sensors. Single-chip channel fusion can be an effective solution, while it is challenging to suppress the noise and integrate massive I/O pads. However, conventional oversampling noise-shaping methods increase power consumption, which fails to meet the demand of long-term monitoring applications. In addition, existing R/C sensor-interface chips require a pair of I/O pads for each sensor, where the pad frame dominates the overall chip area in massive-channel integration. In this work, we demonstrate a 72-channel R&C sensor-interface chip for proximity-and-temperature sensing. A noise-orthogonalizing technique is proposed to eliminate the quantization noise at the signal frequencies, achieving an energy efficiency of 19.1 pJ/step/channel. Moreover, a pad-sharing technique is proposed to reduce the number of I/O pads by half, enabling 72 sensors to be read by 36 pairs of I/O pads. The chip is fabricated by 65-nm CMOS technology, and measurement results show resolutions of 286 Omega and 162 fF, respectively. The power consumption and die area are reduced to 0.74 mu text{W} /Channel and 0.038 mm2/Channel, respectively.

The size of wireless systems is required to be reduced in many applications, such as ultra-low-power sensor nodes and wearable/implantable devices, where battery and crystal are the two main bottlenecks in system miniaturization. In recent years, battery-free radios based on wireless power transfer (WPT) have shown great potential in miniature wireless systems, while a reliable on-chip clock without a crystal remains a design challenge. Conventional methods utilized the RF WPT tone as the reference for clock generation, but the high RF frequency leads to high power consumption. In comparison, using a lower WPT frequency results in an antenna with a larger size. In this work, the 2nd-order inter-modulation (IM2) component of the two RF WPT tones is extracted to lock an on-chip oscillator, providing a low-jitter PVT-robust clock. In this way, the wireless systems can benefit from: 1) The clock recovery circuits operate at a low IM2 frequency, reducing the power consumption. 2) The WPT can be set to a high RF frequency to minimize the antenna. Fabricated in 65 nm CMOS process, the proposed crystal-less clock generator takes a small area of 0.023 mm2 in a wireless system chip. Measured results show -92 dBc/Hz@10 kHz phase noise and 6.8 μ W power.