Compute-in-memory (CIM) accelerators for spiking neural networks (SNNs) are promising solutions to enable μs-level inference latency and ultra-low energy in edge vision applications. Yet, their current lack of flexibility at both the circuit and system levels prevents their deployment in a wide range of real-life scenarios. In this work, we propose FlexSpIM, a novel digital CIM macro that supports arbitrary operand resolution and shape within a unified CIM storage for weights and membrane potentials. These circuit-level techniques enable a hybrid weight- and output-stationary dataflow at the system level to maximize operand reuse, thereby minimizing costly on- and off-chip data movements during the SNN execution. Measurement results of a fabricated FlexSpIM prototype in 40-nm CMOS demonstrate a 2× increase in 1-bit-normalized energy efficiency compared to prior fixed-precision digital CIM-based SNNs, while providing resolution reconfiguration with bitwise granularity. Our approach can save up to 90% energy in large-scale systems, while reaching a state-of-the-art classification accuracy of 95.8% on the IBM DVS gesture dataset.

This article presents a compact sub-1-V bipolar junction transistor (BJT)-based temperature sensor for thermal management applications. To operate from a sub-1-V supply, two capacitors are first pre-charged to a supply-independent initial voltage (> 1 V) by regulated charge pumps (RCPs) and then discharged through two diode-connected BJTs. By using different discharge times, proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) voltages can be generated. These are then read out by an area-and energy-efficient charge-balancing ΔΣ modulator to generate a digital representation of temperature. To reduce its noise, the modulator's first inverter-based integrator employs both chopping and auto-zeroing. Fabricated in a standard 22-nm bulk CMOS process, the sensor occupies 0.01 mm² and consumes 2.9 μW from a 0.8-V supply. It achieves a 1-point trimmed inaccuracy of ± 0.4 °C (3σ) from -40 °C to 125 °C, which is the best reported in sub-65-nm CMOS. It also achieves high energy efficiency, resulting in a resolution figure of merit (FoM) of 0.41

This article describes a PNP-based temperature sensor that achieves both high energy efficiency and accuracy. Two resistors convert the CTAT and PTAT voltages generated by a PNP-based front-end into two currents whose ratio is then digitized by a continuous-time (CT) Δ Σ -modulator. Chopping and dynamic-element-matching (DEM) are used to mitigate the effects of component mismatch and 1/f noise, while the spread in V _BE and in the ratio of the two resistors is digitally trimmed at room temperature (RT). Fabricated in a 0.18μ m CMOS process, the sensor occupies 0.12 mm ², and draws 9.5μ A from a supply voltage ranging from 1.7 to 2.2 V. Measurements on 40 samples from one batch show that it achieves an inaccuracy of ± 0.1° C (3σ) from -55° C to 125° C, and a commensurate supply sensitivity of only 0.01° C/V. Furthermore, it achieves high energy efficiency, with a resolution Figure of Merit (FoM) of 0.85

This paper presents a direct conversion transceiver intended for use in a microfluidic NMR flowmeter. It consists of an H-bridge power amplifier, which drives a hand-wound milimeter-sized coil with RF signals, and a direct conversion receiver, which amplifies the NMR signals picked up by the coil, and then digitizes them with an asynchronous 8 bit SAR ADC sampling at 70 MHz. Fabricated in a 65 nm CMOS technology, the receiver achieves a noise spectral density of 1 nV/sqrt(Hz) at 21 MHz, while dissipating only 36 mW. A microfluidic flowmeter based on the transceiver and a handheld 0.5 T permanent magnet can measure flow rates up to 96 ml/h in a 0.8 mm inner-diameter channel with pm 1.3 % full-scale error. To the authors' best knowledge, this is the first reported portable NMR flowmeter.

Bias-flip rectifiers are commonly employed for piezoelectric energy harvesting (PEH). This article proposes a synchronized switch harvesting on an inductor (SSHI) rectifier with a duty-cycle-based (DCB) maximum power point tracking (MPPT) algorithm. The proposed DCB MPPT algorithm is based on the mathematically derived relation between the MPPT efficiency and the duty cycle of the bridge rectifier. The resulting equation shows that the MPPT efficiency only depends on the rectifier duty cycle, and is independent of any other system variables, such as voltage bias-flipping efficiency, the open-circuit voltage from the harvester, vibration frequency, etc. As a result, MPPT can be achieved by regulating the duty cycle, simplifying circuit implementation, and achieving self-regulating and continuous MPPT. This design was fabricated in a 180-nm BCD process. The measured results show 98% peak MPPT efficiency and up to 738% output power enhancement.

Advances in CMOS technologies and circuit techniques have led to the development of continuous-time delta-sigma modulators (CTΔ Σ Ms) that sample at gigahertz (GHz) frequencies and achieve high linearity [-100 dBc and >120 dBFS spurious-free dynamic ranges (SFDRs)] in wide bandwidths (>100 MHz). However, at low frequencies (≤ 10 MHz), their performance is limited by the 1/f noise generated by the near-minimum size devices used in their wide-bandwidth input stages. This, in turn, limits their use in radio receivers intended to cover both the AM and FM bands. In this work, a multi-path multi-frequency chopping scheme is proposed to suppress 1/f noise, while preserving interferer robustness, thermal noise levels, and linearity. Implemented in a CTΔ Σ analog-to-digital converter (ADC) sampling at 6 GHz, it achieves a 22× reduction in 1/f noise, as well as 122-dBFS SFDR and -98.3-dBc THD in a 120-MHz BW.

A single-stage dual-output regulating voltage doubler (DOVD) is proposed for biomedical wireless power transfer (WPT) systems. Derived from the full-wave voltage doubler (VD) topology, it achieves ac-to-dc rectification and dual-output voltage regulation in a single stage by using only two power transistors. The DOVD's inherent voltage conversion ratio (VCR) of 2 enhances the overall voltage gain of a WPT system, thus extending the transfer range against varying link conditions. To eliminate cross-regulation between the two outputs and provide fast load-transient responses, a parallel pulse-frequency modulation (PPFM) controller is proposed. In addition, a digital-tuning adaptive delay compensation technique with fast error-variation responses is proposed to achieve soft-switching in the power stage. Implemented in a 180-nm Bipolar-CMOS-DMOS (BCD) technology and operating at 6.78 MHz, the proposed DOVD achieves dual regulated outputs at 1.8 and 3.3 V, a VCR of up to 1.875, and a power conversion efficiency (PCE) of up to 92.95% over an output power range of 2.6-90.5 mW. It also achieves instant load-transient responses and unnoticeable cross-regulation during 25× load transients at both outputs.

This article presents a CMOS temperature sensor that achieves both state-of-the-art energy efficiency and accuracy. An NPN-based front end uses two resistors to efficiently generate a PTAT and CTAT current, whose ratio is then digitized by a continuous-time (CT) Δ Σ -modulator. A β-compensation technique is used to mitigate base current errors associated with the NPN's finite β. Component mismatch and 1/f noise are mitigated by applying chopping and dynamic element matching (DEM), while the spread in V_BE and the ratio of the two resistors are digitally trimmed at room temperature (RT). Fabricated in a 0.18-μ m CMOS process, the sensor draws 2.5μ A from a supply voltage ranging from 1.4 to 2.2 V. Measurements on 40 samples show that it achieves an inaccuracy of ± 0.1° C (3Σ ) from - 55° C to 125° C. Furthermore, it is both highly energy efficient, with a resolution figure of merit (FoM) of 200fJċK² , as well as very compact, occupying only 0.07 mm2.

This article presents a hybrid magnetic current sensor for contactless current measurement. Pick-up coils and Hall plates are employed to sense the high and low-frequency fields, respectively, generated by a current-carrying conductor. Due to the differentiating characteristic of the pick-up coils, a flat frequency response can then be obtained by summing the outputs of the coil and the Hall paths and passing the result through a 1st-order low-pass filter (LPF). For maximum resolution, the LPF corner frequency (2 kHz) is set such that the noise contribution of each path is equal. To suppress the coil-path offset without the use of large ac coupling capacitors, an area-efficient dual dc servo loop (D3SL) is used. This effectively suppresses the coil-path offset, resulting in a total offset of 73 μT , which is mainly dominated by the Hall path. Fabricated in a standard 0.18-μm CMOS process, the current sensor occupies 3.9 mm2 and draws 7.1 mA from a 1.8 V supply. It achieves 43 mA resolution in a 5 MHz bandwidth, which is 1.5 × better than the state-of-the-art hybrid sensors. It also achieves the lowest energy efficiency FoM (3.5 ×) among CMOS magnetic current sensors.

Magnetic current sensors are widely used in applications where galvanic isolation and wide bandwidth (BW) are desired, such as in switched-mode power supplies and motor drivers. By using Hall plates for low frequencies and pick-up coils for high frequencies, hybrid magnetic sensors can achieve high resolution (tens of textmA) over a wide frequency range (up to 15MHz) [1]-[3]. However, previous designs exhibit either poor gain flatness over frequency or limited energy efficiency. This work presents a hybrid magnetic current sensor that textachievespm 1. 1% gain flatness, which is 3times better than prior art [1]-[3]. Its energy efficiency is also 11times better than the state-of-the-art [1], [4], [5].

This article presents the design and implementation of a compact CMOS RC frequency reference. It consists of a frequency-locked loop (FLL) that locks the period of a voltage-controlled oscillator (VCO) to the time an RC network takes to charge to a reference voltage. Conventionally, an RC time constant with a near-zero temperature coefficient (TC) is realized by using a trimmed network of resistors with different TCs. In this work, such a network is used to realize a temperature-dependent reference voltage whose TC cancels that of a single-resistor RC time constant. Compared with the conventional approach, which requires resistors with TCs of opposite polarity, the proposed approach can be implemented with resistors with TCs of similar polarity, and so it can be implemented in most CMOS processes. To compensate for RC spread, a trimmed capacitor is used to adjust the nominal frequency. Two prototype chips were made, one based on p- /n-polysilicon resistors and other based on silicided/p-diffusion resistors. Fabricated in a standard 180-nm CMOS technology, the polysilicon-based prototype has an active area of 0.01 mm2 and an absolute inaccuracy of ±2800 ppm from -45 °C to 125 °C with a fixed TC-trim and a one-point frequency trim. After one week of accelerated aging at 150 °C, however, significant drift (5000 ppm) was observed. The diffusion-based prototype exhibits greater inaccuracy (±14 400 ppm) but much less drift (600 ppm).

There has been a long-standing interest in controlling and instrumenting the human body. Whether to restore lost function with neural prosthetics, monitor blood glucose levels, or augment human capabilities, there are countless opportunities for sensors inside ( e.g., ingestible, injectable, and implantable) and outside ( e.g., wearable) the body. However, many challenges exist when instrumenting the body. First, many use cases ( e.g., implanted sensors) require long-term recording to capture anomalous behavior—sometimes with limited accessibility—necessitating ultralow power consumption. Second, the power reduction challenge is further exacerbated by size constraints, which limit battery capacity or harvestable energy levels. Third, the signals of interest are often low bandwidth (kHz) and small in amplitude (µV to mV); thus, low-noise front ends are needed. Addressing these challenges has led to a large body of work on the design of highly power-efficient, low-noise amplifiers for biomedical integrated circuits.

This paper presents a nano-power high-side shunt-based current sensor (CS) that digitizes the voltage drop across an on-chip (±1A) or a lead-frame (±30A) shunt. A TC-tunable ADC reference compensates for the shunts' large temperature coefficient (TC), resulting in ±0.5% gain error from -40 to 85°C. The CS employs a capacitively coupled gm-boosted front-end followed by a CCO-based Δ Σ ADC. Together with a floating input chopper, this results in an input common-mode range (ICMR) of 0-to-15V, the largest reported for a CS implemented in a standard CMOS process. It achieves high energy efficiency (164dB FoM) while consuming only 720nW, representing a 4 × improvement on the state-of-the-art and making this the first ever reported sub-μ W smart current sensor.

CMOS frequency references based on RC oscillators are usually preferred over bulky crystals in loT applications [1-5]. However, due to the process spread and finite temperature coefficient (TC) of most on-chip resistors, RC oscillators require trimming and temperature compensation to achieve decent accuracy. Enabled by high-resolution trimming techniques such as DeltaSigma [1], [2] or pulse-density [3] modulation, recent designs can obtain good accuracy (<0.1 %) at the expense of large chip area. However, existing compact (<0.02mm2) designs suffer from frequency errors in the order of 1% or more [4], [5]. Moreover, their temperature compensation schemes usually require the use of resistors with complementary TCs, which are not available in all CMOS technologies.

This article presents a digital-input class-D amplifier (CDA) achieving high dynamic range (DR) by employing a chopped capacitive feedback network and a capacitive digital-to-analog converter (DAC). Compared with conventional resistive-feedback CDAs driven by resistive or current-steering DACs, the proposed architecture eliminates the noise from the DAC and feedback resistors. Intermodulation between the chopping, pulsewidth modulation (PWM), and DAC sampling frequency is analyzed to avoid negative impacts on the DR and linearity. Real-time dynamic element matching (RTDEM) is employed to address distortion due to mismatch in the DAC, while its intersymbol interference (ISI) is eliminated by deadbanding. The prototype, implemented in a 180-nm bipolar, CMOS, and DMOS (BCD) process, achieves 120.9 dB of DR and a peak total harmonic distortion plus noise (THD+N) of-111.2 dB. It can drive a maximum of 15/26 W into an 8-/4-Ω load with a peak efficiency of 90%/86%.

This article presents a hybrid magnetic current sensor for galvanically isolated measurements. It consists of a CMOS chip that senses the magnetic field generated by current flowing through a lead-frame-based current rail. Hall plates and coils are used to sense low-frequency (dc to 10 kHz) and high-frequency (10 kHz to 5 MHz) magnetic fields, respectively. With the help of on- chip calibration coils, the biasing current of the Hall plates is trimmed to match the sensitivity of the Hall and coil signal paths. The sensitivity drift of the coil path with temperature is compensated by using temperature-dependent gain-setting resistors, while the drift of the Hall path is compensated by biasing the Hall plates with a proportional- to-absolute-temperature (PTAT) current. The resulting sensitivity drift is less than 9% from-40 °C to 80 °C. The offset of the Hall plates is reduced by the current spinning technique, and the resulting ripple is suppressed by a multiplexed ripple-reduction loop (MMRL). Fabricated in a standard 0.18-μm CMOS process, the current sensor occupies 4.6 mm2 and draws 7.8 mA from a 1.8-V supply. It achieves a gain variation of only ±2% in a 5-MHz BW. It also achieves high energy efficiency, with an figure of merit (FoM) of 1.6 fW/Hz.

Probably the most distinct divide in electronic circuits is that between digital and linear (analog) circuits. Using vacuum tubes; later, transistors; and then ICs, circuits based on switching (binary and digital signals) and amplification (analog signals) have always been at the heart of electronic systems. Even though electronics are making our world more digital, the real world remains stubbornly analog. Circuits for interfacing sensors and driving actuators, amplifying (weak) analog signals, manipulating these signals through analog signal processing, and, finally, converting them into the digital domain and vice versa were, are, and will remain fundamental research and development fields in circuit design. Due to the wide scope of the field, ranging from RF circuits, power management, reference generation, filter design, and oscillators to comparators and other nonlinear circuits, just to name a few, it is clear that a short review article cannot possibly mention all topics, let alone cover them all. So, choices were made. We begin this article with amplifiers, which are one of the critical analog building blocks that often determine system performance. We briefly review the early days of IC-based amplifiers and some outstanding circuit innovations for amplifier design. Thereafter, we highlight the history and state of the art of ADCs, their architectures, and efficiency improvements over four decades. Finally, we review sensor interfaces, first with a general focus on their history and the state of the art of various sensor modalities and, second, with a special focus on biomedical interface circuits for biopotential recording in the context of neural amplifiers. With this variety of topics, we intend to highlight the importance of the transistor and analog ICs to the world as we know it today.

This article presents a sub-1 V bipolar junction transistor (BJT)-based temperature sensor that achieves both high accuracy and high energy efficiency. To avoid the extra headroom required by conventional current sources, the sensor’s diode-connected BJTs are biased by precharging sampling capacitors to the supply voltage and then discharging them through the BJTs. This capacitive biasing technique requires little headroom ( ∼ 150 mV), and simultaneously samples the BJTs’ base–emitter voltages. The latter are then applied to a switched-capacitor (SC) ΔΣ ADC to generate a digital representation of temperature. For robust sub-1 V operation and high energy efficiency, the ADC employs auto-zeroed inverter-based integrators. Fabricated in a standard 0.18- μ m CMOS process, the sensor occupies 0.25 mm 2 and consumes 810 nW from a 0.95-V supply at room temperature. It achieves an inaccuracy of ± 0.15 ∘ C (3 σ ) from − 55 ∘ C to 125 ∘ C after a 1-point trim, which is at par with the state-of-the-art. It also achieves a resolution figure of merit (FoM) of 0.34 pJ ⋅ K 2 , which is more than 6 × lower than that of state-of-the-art BJT-based sensors with similar accuracy.

BJT-based temperature sensors are widely used because they can achieve excellent accuracy after 1-point calibration. However, they typically dissipate mu textWs of power and require supply voltages above 1V [1]. Although sensors based on DTMOSTs [2], [3], capacitively biased (CB) diodes and BJTs [4,5] have demonstrated sub-1V operation, this comes at the expense of accuracy. This paper presents a sub-1V CB BJT-based temperature sensor that achieves a 1-point-trimmed inaccuracy of 0.15°C (3σ) from -55 circC to 125 circC, which is 4times better than the CB BJT state-of-the-art [4]. It also achieves a resolution FoM of 0.34pJ.K2, which is 6.8 times better than that of state-of-the-art BJT-based sensors with a similar accuracy [1], [6], (Fig. 23.5.6).