This article presents a compact sub-1-V bipolar junction transistor (BJT)-based temperature sensor for thermal management applications. To operate from a sub-1-V supply, two capacitors are first pre-charged to a supply-independent initial voltage (> 1 V) by regulated charge pumps (RCPs) and then discharged through two diode-connected BJTs. By using different discharge times, proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) voltages can be generated. These are then read out by an area-and energy-efficient charge-balancing ΔΣ modulator to generate a digital representation of temperature. To reduce its noise, the modulator's first inverter-based integrator employs both chopping and auto-zeroing. Fabricated in a standard 22-nm bulk CMOS process, the sensor occupies 0.01 mm² and consumes 2.9 μW from a 0.8-V supply. It achieves a 1-point trimmed inaccuracy of ± 0.4 °C (3σ) from -40 °C to 125 °C, which is the best reported in sub-65-nm CMOS. It also achieves high energy efficiency, resulting in a resolution figure of merit (FoM) of 0.41

Compute-in-memory (CIM) accelerators for spiking neural networks (SNNs) are promising solutions to enable μs-level inference latency and ultra-low energy in edge vision applications. Yet, their current lack of flexibility at both the circuit and system levels prevents their deployment in a wide range of real-life scenarios. In this work, we propose FlexSpIM, a novel digital CIM macro that supports arbitrary operand resolution and shape within a unified CIM storage for weights and membrane potentials. These circuit-level techniques enable a hybrid weight- and output-stationary dataflow at the system level to maximize operand reuse, thereby minimizing costly on- and off-chip data movements during the SNN execution. Measurement results of a fabricated FlexSpIM prototype in 40-nm CMOS demonstrate a 2× increase in 1-bit-normalized energy efficiency compared to prior fixed-precision digital CIM-based SNNs, while providing resolution reconfiguration with bitwise granularity. Our approach can save up to 90% energy in large-scale systems, while reaching a state-of-the-art classification accuracy of 95.8% on the IBM DVS gesture dataset.

This article describes the design and implementation of a compact CMOS RC frequency reference based on N-type diffusion (N-diff) resistors and metal-insulator-metal (MIM) capacitors. It consists of a frequency-locked loop (FLL) that locks the period of a voltage-controlled oscillator (VCO) to the time it takes a current source to charge a capacitor to a reference voltage. Conventionally, the temperature compensation of such FLLs involves the use of resistors with different temperature dependencies. In this work, however, this is done by using two bipolar junction transistor (BJT)-based current sources with different temperature dependencies to charge a MIM capacitor and generate a reference voltage across an N-diff resistor, respectively. Implemented in a standard 180-nm technology, the resulting frequency reference achieves small size (0.028 mm²), moderate inaccuracy (±900 ppm) from -40 ^°C to 125 ^°C, and low drift (±1600 ppm) after accelerated aging. The versatility of the proposed temperature compensation scheme is validated by replacing the N-diff resistor with a P-poly resistor. However, the latter exhibits greater inaccuracy (+2000/-2500 ppm) and more drift (-2600/-8100 ppm) after accelerated aging.

This article presents a CMOS temperature sensor that achieves both state-of-the-art energy efficiency and accuracy. An NPN-based front end uses two resistors to efficiently generate a PTAT and CTAT current, whose ratio is then digitized by a continuous-time (CT) Δ Σ -modulator. A β-compensation technique is used to mitigate base current errors associated with the NPN's finite β. Component mismatch and 1/f noise are mitigated by applying chopping and dynamic element matching (DEM), while the spread in V_BE and the ratio of the two resistors are digitally trimmed at room temperature (RT). Fabricated in a 0.18-μ m CMOS process, the sensor draws 2.5μ A from a supply voltage ranging from 1.4 to 2.2 V. Measurements on 40 samples show that it achieves an inaccuracy of ± 0.1° C (3Σ ) from - 55° C to 125° C. Furthermore, it is both highly energy efficient, with a resolution figure of merit (FoM) of 200fJċK² , as well as very compact, occupying only 0.07 mm2.

This brief presents a capacitively-biased CMOS voltage reference, which can operate from a sub-1V supply while achieving a low temperature coefficient (TC) and a competitive power-supply rejection ratio (PSRR). The reference voltage is generated by a capacitive bias circuit that provides a well-defined proportional-to-absolute-temperature (PTAT) bias current for a ΔVth type reference that consists of two stacked MOSFETs with different threshold voltages. The generated output voltage is sampled by an auto-zeroed (AZ) buffer, which can drive capacitive loads up to 2 nF. Fabricated in a 65 nm CMOS process, the prototype voltage reference occupies 0.058 mm2, including the AZ buffer and an on-chip timing generator. It outputs a reference voltage of 204.1 mV with a minimum supply voltage of 0.7 V. It achieves a TC of 18 ppm/° C from -40 ° C to 85 ° C and a PSRR of -75 dB at 100 Hz with only 200 μV ripple.

Advances in CMOS technologies and circuit techniques have led to the development of continuous-time delta-sigma modulators (CTΔ Σ Ms) that sample at gigahertz (GHz) frequencies and achieve high linearity [-100 dBc and >120 dBFS spurious-free dynamic ranges (SFDRs)] in wide bandwidths (>100 MHz). However, at low frequencies (≤ 10 MHz), their performance is limited by the 1/f noise generated by the near-minimum size devices used in their wide-bandwidth input stages. This, in turn, limits their use in radio receivers intended to cover both the AM and FM bands. In this work, a multi-path multi-frequency chopping scheme is proposed to suppress 1/f noise, while preserving interferer robustness, thermal noise levels, and linearity. Implemented in a CTΔ Σ analog-to-digital converter (ADC) sampling at 6 GHz, it achieves a 22× reduction in 1/f noise, as well as 122-dBFS SFDR and -98.3-dBc THD in a 120-MHz BW.

This article describes a PNP-based temperature sensor that achieves both high energy efficiency and accuracy. Two resistors convert the CTAT and PTAT voltages generated by a PNP-based front-end into two currents whose ratio is then digitized by a continuous-time (CT) Δ Σ -modulator. Chopping and dynamic-element-matching (DEM) are used to mitigate the effects of component mismatch and 1/f noise, while the spread in V _BE and in the ratio of the two resistors is digitally trimmed at room temperature (RT). Fabricated in a 0.18μ m CMOS process, the sensor occupies 0.12 mm ², and draws 9.5μ A from a supply voltage ranging from 1.7 to 2.2 V. Measurements on 40 samples from one batch show that it achieves an inaccuracy of ± 0.1° C (3σ) from -55° C to 125° C, and a commensurate supply sensitivity of only 0.01° C/V. Furthermore, it achieves high energy efficiency, with a resolution Figure of Merit (FoM) of 0.85

This paper presents a direct conversion transceiver intended for use in a microfluidic NMR flowmeter. It consists of an H-bridge power amplifier, which drives a hand-wound milimeter-sized coil with RF signals, and a direct conversion receiver, which amplifies the NMR signals picked up by the coil, and then digitizes them with an asynchronous 8 bit SAR ADC sampling at 70 MHz. Fabricated in a 65 nm CMOS technology, the receiver achieves a noise spectral density of 1 nV/sqrt(Hz) at 21 MHz, while dissipating only 36 mW. A microfluidic flowmeter based on the transceiver and a handheld 0.5 T permanent magnet can measure flow rates up to 96 ml/h in a 0.8 mm inner-diameter channel with pm 1.3 % full-scale error. To the authors' best knowledge, this is the first reported portable NMR flowmeter.

This article presents a 14-bit fully dynamic sensor interface that consists of a switched-capacitor (SC) ΔΣ modulator and a dynamic bandgap reference (BGR). The BGR is implemented by summing the proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) outputs of two PNP-based capacitive DACs. At the sampling rate, the DAC capacitors are pre-charged to the supply and then discharged for a fixed period via PNPs, thus biasing them and simultaneously sampling their base-emitter voltages. By using the modulator's first integrator to sum the DAC outputs, a dynamic BGR can be realized, which does not need additional reference buffers or decoupling capacitors. To make the system fully dynamic, the modulator itself is based on capacitively biased (CB) floating inverter amplifiers (FIAs). Implemented in a standard 130-nm CMOS process, the sensor interface occupies an area of 0.2 mm². It achieves an SNDR of > 84.5 dB over a scalable bandwidth (BW) ranging from 98 Hz to 5.9 kHz while consuming 1.7-50.8 μW. Furthermore, by employing a time-domain temperature-compensation scheme, it achieves a batch-trimmed gain error of ± 0.26% from -40°C to 125 °C.

A single-stage dual-output regulating voltage doubler (DOVD) is proposed for biomedical wireless power transfer (WPT) systems. Derived from the full-wave voltage doubler (VD) topology, it achieves ac-to-dc rectification and dual-output voltage regulation in a single stage by using only two power transistors. The DOVD's inherent voltage conversion ratio (VCR) of 2 enhances the overall voltage gain of a WPT system, thus extending the transfer range against varying link conditions. To eliminate cross-regulation between the two outputs and provide fast load-transient responses, a parallel pulse-frequency modulation (PPFM) controller is proposed. In addition, a digital-tuning adaptive delay compensation technique with fast error-variation responses is proposed to achieve soft-switching in the power stage. Implemented in a 180-nm Bipolar-CMOS-DMOS (BCD) technology and operating at 6.78 MHz, the proposed DOVD achieves dual regulated outputs at 1.8 and 3.3 V, a VCR of up to 1.875, and a power conversion efficiency (PCE) of up to 92.95% over an output power range of 2.6-90.5 mW. It also achieves instant load-transient responses and unnoticeable cross-regulation during 25× load transients at both outputs.

Bias-flip rectifiers are commonly employed for piezoelectric energy harvesting (PEH). This article proposes a synchronized switch harvesting on an inductor (SSHI) rectifier with a duty-cycle-based (DCB) maximum power point tracking (MPPT) algorithm. The proposed DCB MPPT algorithm is based on the mathematically derived relation between the MPPT efficiency and the duty cycle of the bridge rectifier. The resulting equation shows that the MPPT efficiency only depends on the rectifier duty cycle, and is independent of any other system variables, such as voltage bias-flipping efficiency, the open-circuit voltage from the harvester, vibration frequency, etc. As a result, MPPT can be achieved by regulating the duty cycle, simplifying circuit implementation, and achieving self-regulating and continuous MPPT. This design was fabricated in a 180-nm BCD process. The measured results show 98% peak MPPT efficiency and up to 738% output power enhancement.

This article presents a hybrid magnetic current sensor for contactless current measurement. Pick-up coils and Hall plates are employed to sense the high and low-frequency fields, respectively, generated by a current-carrying conductor. Due to the differentiating characteristic of the pick-up coils, a flat frequency response can then be obtained by summing the outputs of the coil and the Hall paths and passing the result through a 1st-order low-pass filter (LPF). For maximum resolution, the LPF corner frequency (2 kHz) is set such that the noise contribution of each path is equal. To suppress the coil-path offset without the use of large ac coupling capacitors, an area-efficient dual dc servo loop (D3SL) is used. This effectively suppresses the coil-path offset, resulting in a total offset of 73 μT , which is mainly dominated by the Hall path. Fabricated in a standard 0.18-μm CMOS process, the current sensor occupies 3.9 mm2 and draws 7.1 mA from a 1.8 V supply. It achieves 43 mA resolution in a 5 MHz bandwidth, which is 1.5 × better than the state-of-the-art hybrid sensors. It also achieves the lowest energy efficiency FoM (3.5 ×) among CMOS magnetic current sensors.

Class-D amplifiers (CDAs) are widely used in audio applications where a high power efficiency is required. As most audio sources are digital nowadays, implementing digital-input CDAs results in higher levels of integration and lower cost. However, prior open-loop digital-input CDAs suffer from high jitter sensitivity and output-stage distortion. In [1], jitter sensitivity at small signal levels is mitigated using a buck-boost converter that adaptively lowers the supply at the expense of extra external components and reduced power efficiency. Prior closed-loop digital-input CDAs employing multi-bit current-steering [2] or resistive [3] DACs are less sensitive to jitter, but their DR is limited to about 115dB. DAC non-idealities and intermodulation distortion are also challenges, and prior works only achieved a peak textTHD+N of about -98textdB [2], [3]. This paper presents a digital-input CDA that achieves high DR by combining a low-noise capacitive DAC (CDAC) with dedicated techniques to mitigate DAC mismatch, lSI, and intermodulation distortion. A prototype implemented in a 0.18mum BCD process achieves 120.9dB DR and -111.2textdB peak textTHD+N. Furthermore, it can deliver 13W/23W at 10% THD into an 8Omega/4Omega load with a 90%/86% efficiency.

This paper presents a nano-power high-side shunt-based current sensor (CS) that digitizes the voltage drop across an on-chip (±1A) or a lead-frame (±30A) shunt. A TC-tunable ADC reference compensates for the shunts' large temperature coefficient (TC), resulting in ±0.5% gain error from -40 to 85°C. The CS employs a capacitively coupled gm-boosted front-end followed by a CCO-based Δ Σ ADC. Together with a floating input chopper, this results in an input common-mode range (ICMR) of 0-to-15V, the largest reported for a CS implemented in a standard CMOS process. It achieves high energy efficiency (164dB FoM) while consuming only 720nW, representing a 4 × improvement on the state-of-the-art and making this the first ever reported sub-μ W smart current sensor.

CMOS frequency references based on RC oscillators are usually preferred over bulky crystals in loT applications [1-5]. However, due to the process spread and finite temperature coefficient (TC) of most on-chip resistors, RC oscillators require trimming and temperature compensation to achieve decent accuracy. Enabled by high-resolution trimming techniques such as DeltaSigma [1], [2] or pulse-density [3] modulation, recent designs can obtain good accuracy (<0.1 %) at the expense of large chip area. However, existing compact (<0.02mm2) designs suffer from frequency errors in the order of 1% or more [4], [5]. Moreover, their temperature compensation schemes usually require the use of resistors with complementary TCs, which are not available in all CMOS technologies.

Advances in CMOS technologies have led to the development of continuous-time ΔΣ modulators (CTDSMs) with GHz sampling rates that achieve better than-100dBc linearity and bandwidths above 100MHz. However, at low frequencies (below 10MHz), their SNDR is limited by 1/f noise, which limits their use in radio receivers intended to cover both the AM and the FM bands. In this work, a multi-path multi-frequency chopping scheme is proposed to suppress 1/f noise, while maintaining interferer robustness, noise, spurious, and linearity performance. Implemented in a CTDSM sampling at 6GHz, it reduces its 1/f noise corner frequency by 22x and achieves -98.3dBc THD, 122dBFS SFDR in 120MHzBW.

This article presents a hybrid magnetic current sensor for galvanically isolated measurements. It consists of a CMOS chip that senses the magnetic field generated by current flowing through a lead-frame-based current rail. Hall plates and coils are used to sense low-frequency (dc to 10 kHz) and high-frequency (10 kHz to 5 MHz) magnetic fields, respectively. With the help of on- chip calibration coils, the biasing current of the Hall plates is trimmed to match the sensitivity of the Hall and coil signal paths. The sensitivity drift of the coil path with temperature is compensated by using temperature-dependent gain-setting resistors, while the drift of the Hall path is compensated by biasing the Hall plates with a proportional- to-absolute-temperature (PTAT) current. The resulting sensitivity drift is less than 9% from-40 °C to 80 °C. The offset of the Hall plates is reduced by the current spinning technique, and the resulting ripple is suppressed by a multiplexed ripple-reduction loop (MMRL). Fabricated in a standard 0.18-μm CMOS process, the current sensor occupies 4.6 mm2 and draws 7.8 mA from a 1.8-V supply. It achieves a gain variation of only ±2% in a 5-MHz BW. It also achieves high energy efficiency, with an figure of merit (FoM) of 1.6 fW/Hz.

Synchronized bias-flip rectifiers, such as synchronized switch harvesting on inductor (SSHI) rectifiers, are widely used for piezoelectric energy harvesting (PEH) [1], which can replace the use of batteries in many loT applications, thus reducing both system volume and maintenance cost. However, the output power extracted by such rectifiers strongly depends on the impedance matching between the piezoelectric transducer (PT) and the circuit. To maximize this, two maximum power point tracking (MPPT) algorithms are often used. As shown in Fig. 30.3.1 (left), the Perturb & Observe (P&O) (a.k.a. hill-climbing) algorithm adjusts the rectified output power in a stepwise manner towards the maximum power point (MPP), thus establishing robust and continuous MPPT. However, accurately sensing the rectified output power often requires complex and power-hungry hardware [1], [2]. Another simpler algorithm is based on the fractional open-circuit voltage (FOCV) and involves periodically measuring the PT's open-circuit voltage amplitude (VOC) and regulating the rectified voltage (VREC) to a level (VMPP), which corresponds to the MPP [3-6]. However, the PT must be periodically disconnected from the rectifier to measure VOC, resulting in wasted energy, while the inherent delay in sensing VOC variations reduces the overall tracking efficiency. Furthermore, a calibration step is usually necessary to determine VMPP, since this depends on the actual PT voltage flip efficiency (etaF) of the bias-flip rectifier.

This article presents a digital-input class-D amplifier (CDA) achieving high dynamic range (DR) by employing a chopped capacitive feedback network and a capacitive digital-to-analog converter (DAC). Compared with conventional resistive-feedback CDAs driven by resistive or current-steering DACs, the proposed architecture eliminates the noise from the DAC and feedback resistors. Intermodulation between the chopping, pulsewidth modulation (PWM), and DAC sampling frequency is analyzed to avoid negative impacts on the DR and linearity. Real-time dynamic element matching (RTDEM) is employed to address distortion due to mismatch in the DAC, while its intersymbol interference (ISI) is eliminated by deadbanding. The prototype, implemented in a 180-nm bipolar, CMOS, and DMOS (BCD) process, achieves 120.9 dB of DR and a peak total harmonic distortion plus noise (THD+N) of-111.2 dB. It can drive a maximum of 15/26 W into an 8-/4-Ω load with a peak efficiency of 90%/86%.