Compute-in-memory (CIM) accelerators for spiking neural networks (SNNs) are promising solutions to enable μs-level inference latency and ultra-low energy in edge vision applications. Yet, their current lack of flexibility at both the circuit and system levels prevents their deployment in a wide range of real-life scenarios. In this work, we propose FlexSpIM, a novel digital CIM macro that supports arbitrary operand resolution and shape within a unified CIM storage for weights and membrane potentials. These circuit-level techniques enable a hybrid weight- and output-stationary dataflow at the system level to maximize operand reuse, thereby minimizing costly on- and off-chip data movements during the SNN execution. Measurement results of a fabricated FlexSpIM prototype in 40-nm CMOS demonstrate a 2× increase in 1-bit-normalized energy efficiency compared to prior fixed-precision digital CIM-based SNNs, while providing resolution reconfiguration with bitwise granularity. Our approach can save up to 90% energy in large-scale systems, while reaching a state-of-the-art classification accuracy of 95.8% on the IBM DVS gesture dataset.

This article describes the design and implementation of a compact CMOS RC frequency reference based on N-type diffusion (N-diff) resistors and metal-insulator-metal (MIM) capacitors. It consists of a frequency-locked loop (FLL) that locks the period of a voltage-controlled oscillator (VCO) to the time it takes a current source to charge a capacitor to a reference voltage. Conventionally, the temperature compensation of such FLLs involves the use of resistors with different temperature dependencies. In this work, however, this is done by using two bipolar junction transistor (BJT)-based current sources with different temperature dependencies to charge a MIM capacitor and generate a reference voltage across an N-diff resistor, respectively. Implemented in a standard 180-nm technology, the resulting frequency reference achieves small size (0.028 mm²), moderate inaccuracy (±900 ppm) from -40 ^°C to 125 ^°C, and low drift (±1600 ppm) after accelerated aging. The versatility of the proposed temperature compensation scheme is validated by replacing the N-diff resistor with a P-poly resistor. However, the latter exhibits greater inaccuracy (+2000/-2500 ppm) and more drift (-2600/-8100 ppm) after accelerated aging.

This paper presents a photovoltaic energy harvesting (PVEH) system achieving both high Maximum Power Point Tracking (MPPT) efficiency ($\eta_{\text {MPPT }}$) and power conversion efficiency ($\left.\eta_{\text {CONV }}\right)$ across a wide input power dynamic range (DR), employing a direct input power-to-digital converter (PDC) and an adaptive power-scalable MPPT scheme. The proposed PVEH achieves $>98 \%$ (with a peak of 99.9 %) $\eta_{\text {MPPT }}$ across a $100,000 \times$ DR $(10 \mu ~\mathrm{W}$ to 1 W), representing a $10 \times$ improvement over the state-of-the-art, as well as a competitive $\eta_{\text{CONV}}$ of $>82 \%$ (with a peak of $\mathbf{9 2 \%}$) across the same DR.

This paper presents a high-accuracy, low-drift 16 MHz RC frequency reference. It is based on a Wien bridge filter that incorporates silicided n-poly resistors and MIM capacitors, whose temperature coefficient is compensated by a PNP-based temperature sensor. After a 2-point trim, it achieves $\pm 350 \text{ppm}$ inaccuracy from $-45^{\circ} \mathrm{C}$ to 85° C, which increases to only $\pm 450$ ppm after accelerated aging. This represents competitive accuracy and state-of-the-art stability for RC-based frequency references, approaching that of their LC-based counterparts while dissipating lower power and occupying less area.

This article presents a compact sub-1-V bipolar junction transistor (BJT)-based temperature sensor for thermal management applications. To operate from a sub-1-V supply, two capacitors are first pre-charged to a supply-independent initial voltage (> 1 V) by regulated charge pumps (RCPs) and then discharged through two diode-connected BJTs. By using different discharge times, proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) voltages can be generated. These are then read out by an area-and energy-efficient charge-balancing ΔΣ modulator to generate a digital representation of temperature. To reduce its noise, the modulator's first inverter-based integrator employs both chopping and auto-zeroing. Fabricated in a standard 22-nm bulk CMOS process, the sensor occupies 0.01 mm² and consumes 2.9 μW from a 0.8-V supply. It achieves a 1-point trimmed inaccuracy of ± 0.4 °C (3σ) from -40 °C to 125 °C, which is the best reported in sub-65-nm CMOS. It also achieves high energy efficiency, resulting in a resolution figure of merit (FoM) of 0.41

This paper presents a direct conversion transceiver intended for use in a microfluidic NMR flowmeter. It consists of an H-bridge power amplifier, which drives a hand-wound milimeter-sized coil with RF signals, and a direct conversion receiver, which amplifies the NMR signals picked up by the coil, and then digitizes them with an asynchronous 8 bit SAR ADC sampling at 70 MHz. Fabricated in a 65 nm CMOS technology, the receiver achieves a noise spectral density of 1 nV/sqrt(Hz) at 21 MHz, while dissipating only 36 mW. A microfluidic flowmeter based on the transceiver and a handheld 0.5 T permanent magnet can measure flow rates up to 96 ml/h in a 0.8 mm inner-diameter channel with pm 1.3 % full-scale error. To the authors' best knowledge, this is the first reported portable NMR flowmeter.

This article presents a CMOS temperature sensor that achieves both state-of-the-art energy efficiency and accuracy. An NPN-based front end uses two resistors to efficiently generate a PTAT and CTAT current, whose ratio is then digitized by a continuous-time (CT) Δ Σ -modulator. A β-compensation technique is used to mitigate base current errors associated with the NPN's finite β. Component mismatch and 1/f noise are mitigated by applying chopping and dynamic element matching (DEM), while the spread in V_BE and the ratio of the two resistors are digitally trimmed at room temperature (RT). Fabricated in a 0.18-μ m CMOS process, the sensor draws 2.5μ A from a supply voltage ranging from 1.4 to 2.2 V. Measurements on 40 samples show that it achieves an inaccuracy of ± 0.1° C (3Σ ) from - 55° C to 125° C. Furthermore, it is both highly energy efficient, with a resolution figure of merit (FoM) of 200fJċK² , as well as very compact, occupying only 0.07 mm2.

This article presents a 14-bit fully dynamic sensor interface that consists of a switched-capacitor (SC) ΔΣ modulator and a dynamic bandgap reference (BGR). The BGR is implemented by summing the proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) outputs of two PNP-based capacitive DACs. At the sampling rate, the DAC capacitors are pre-charged to the supply and then discharged for a fixed period via PNPs, thus biasing them and simultaneously sampling their base-emitter voltages. By using the modulator's first integrator to sum the DAC outputs, a dynamic BGR can be realized, which does not need additional reference buffers or decoupling capacitors. To make the system fully dynamic, the modulator itself is based on capacitively biased (CB) floating inverter amplifiers (FIAs). Implemented in a standard 130-nm CMOS process, the sensor interface occupies an area of 0.2 mm². It achieves an SNDR of > 84.5 dB over a scalable bandwidth (BW) ranging from 98 Hz to 5.9 kHz while consuming 1.7-50.8 μW. Furthermore, by employing a time-domain temperature-compensation scheme, it achieves a batch-trimmed gain error of ± 0.26% from -40°C to 125 °C.

This article describes a PNP-based temperature sensor that achieves both high energy efficiency and accuracy. Two resistors convert the CTAT and PTAT voltages generated by a PNP-based front-end into two currents whose ratio is then digitized by a continuous-time (CT) Δ Σ -modulator. Chopping and dynamic-element-matching (DEM) are used to mitigate the effects of component mismatch and 1/f noise, while the spread in V _BE and in the ratio of the two resistors is digitally trimmed at room temperature (RT). Fabricated in a 0.18μ m CMOS process, the sensor occupies 0.12 mm ², and draws 9.5μ A from a supply voltage ranging from 1.7 to 2.2 V. Measurements on 40 samples from one batch show that it achieves an inaccuracy of ± 0.1° C (3σ) from -55° C to 125° C, and a commensurate supply sensitivity of only 0.01° C/V. Furthermore, it achieves high energy efficiency, with a resolution Figure of Merit (FoM) of 0.85

Advances in CMOS technologies and circuit techniques have led to the development of continuous-time delta-sigma modulators (CTΔ Σ Ms) that sample at gigahertz (GHz) frequencies and achieve high linearity [-100 dBc and >120 dBFS spurious-free dynamic ranges (SFDRs)] in wide bandwidths (>100 MHz). However, at low frequencies (≤ 10 MHz), their performance is limited by the 1/f noise generated by the near-minimum size devices used in their wide-bandwidth input stages. This, in turn, limits their use in radio receivers intended to cover both the AM and FM bands. In this work, a multi-path multi-frequency chopping scheme is proposed to suppress 1/f noise, while preserving interferer robustness, thermal noise levels, and linearity. Implemented in a CTΔ Σ analog-to-digital converter (ADC) sampling at 6 GHz, it achieves a 22× reduction in 1/f noise, as well as 122-dBFS SFDR and -98.3-dBc THD in a 120-MHz BW.

This brief presents a capacitively-biased CMOS voltage reference, which can operate from a sub-1V supply while achieving a low temperature coefficient (TC) and a competitive power-supply rejection ratio (PSRR). The reference voltage is generated by a capacitive bias circuit that provides a well-defined proportional-to-absolute-temperature (PTAT) bias current for a ΔVth type reference that consists of two stacked MOSFETs with different threshold voltages. The generated output voltage is sampled by an auto-zeroed (AZ) buffer, which can drive capacitive loads up to 2 nF. Fabricated in a 65 nm CMOS process, the prototype voltage reference occupies 0.058 mm2, including the AZ buffer and an on-chip timing generator. It outputs a reference voltage of 204.1 mV with a minimum supply voltage of 0.7 V. It achieves a TC of 18 ppm/° C from -40 ° C to 85 ° C and a PSRR of -75 dB at 100 Hz with only 200 μV ripple.

A single-stage dual-output regulating voltage doubler (DOVD) is proposed for biomedical wireless power transfer (WPT) systems. Derived from the full-wave voltage doubler (VD) topology, it achieves ac-to-dc rectification and dual-output voltage regulation in a single stage by using only two power transistors. The DOVD's inherent voltage conversion ratio (VCR) of 2 enhances the overall voltage gain of a WPT system, thus extending the transfer range against varying link conditions. To eliminate cross-regulation between the two outputs and provide fast load-transient responses, a parallel pulse-frequency modulation (PPFM) controller is proposed. In addition, a digital-tuning adaptive delay compensation technique with fast error-variation responses is proposed to achieve soft-switching in the power stage. Implemented in a 180-nm Bipolar-CMOS-DMOS (BCD) technology and operating at 6.78 MHz, the proposed DOVD achieves dual regulated outputs at 1.8 and 3.3 V, a VCR of up to 1.875, and a power conversion efficiency (PCE) of up to 92.95% over an output power range of 2.6-90.5 mW. It also achieves instant load-transient responses and unnoticeable cross-regulation during 25× load transients at both outputs.

Bias-flip rectifiers are commonly employed for piezoelectric energy harvesting (PEH). This article proposes a synchronized switch harvesting on an inductor (SSHI) rectifier with a duty-cycle-based (DCB) maximum power point tracking (MPPT) algorithm. The proposed DCB MPPT algorithm is based on the mathematically derived relation between the MPPT efficiency and the duty cycle of the bridge rectifier. The resulting equation shows that the MPPT efficiency only depends on the rectifier duty cycle, and is independent of any other system variables, such as voltage bias-flipping efficiency, the open-circuit voltage from the harvester, vibration frequency, etc. As a result, MPPT can be achieved by regulating the duty cycle, simplifying circuit implementation, and achieving self-regulating and continuous MPPT. This design was fabricated in a 180-nm BCD process. The measured results show 98% peak MPPT efficiency and up to 738% output power enhancement.

CMOS frequency references based on RC oscillators are usually preferred over bulky crystals in loT applications [1-5]. However, due to the process spread and finite temperature coefficient (TC) of most on-chip resistors, RC oscillators require trimming and temperature compensation to achieve decent accuracy. Enabled by high-resolution trimming techniques such as DeltaSigma [1], [2] or pulse-density [3] modulation, recent designs can obtain good accuracy (<0.1 %) at the expense of large chip area. However, existing compact (<0.02mm2) designs suffer from frequency errors in the order of 1% or more [4], [5]. Moreover, their temperature compensation schemes usually require the use of resistors with complementary TCs, which are not available in all CMOS technologies.

BJT-based temperature sensors are widely used due to their high accuracy over a wide temperature range with a low-cost 1-point trim. Although resistor-based sensors can achieve better energy efficiency, they typically require a 2-point trim to achieve comparable accuracy, while thermal-diffusivity based sensors achieve superior accuracy at the cost of energy efficiency [1]. This paper presents a BJT-based temperature sensor that achieves both excellent accuracy and energy efficiency. To avoid the kTfC noise limitations of conventional discrete-time (OT) readout schemes [2], [3], it employs a compact continuous-time (CT) front-end. Component mismatch, which often limits the accuracy of CT front-ends [4], [5], is mitigated by a combination of dynamic element matching (OEM) and a low-cost resistor-ratio self-calibration scheme. As a result, the sensor achieves a resolution FoM of 0.85textpJcdotK 2, and a competitive inaccuracy of pm 0.1 circC (3sigma) from -55 circC tO 125 circC after a 1-point trim. This makes it 4times more energy-efficient than state-of-the-art BJT-based sensors with similar accuracy [2], [4], [5].

Dual-output regulating rectifier is highly desired in wireless power transfer (WPT) for sub-100mW bioimplants. Such rectifiers perform voltage rectification and dual-output regulation simultaneously, thus avoiding post DC-DC conversions and cascaded power losses [1 –4]. However, the conventional dual-output structure suffers from a low voltage conversion ratio (VCR) (< 1) due to the full bridge rectifier (FBR) topology (Fig. 1), severely limiting the receiver operation when wireless link condition varies [1–2]. In order to extend the operational range without increasing the power demand from the transmitter, [3] presents a charge-pump based dual-output rectifier; however, it uses 10 power transistors (PTs) and 8 off-chip capacitors, degrading the power conversion efficiency (PCE) and increasing the integration cost. Alternatively, the current-mode dual-output rectifier can realize a VCR higher than 1, but the output power is limited to less than 10mW [4], which is insufficient for advanced bioimplants. In this work, a 13. 56MHz single-stage dual-output voltage doubler (DOVD) is proposed to address the above limitations, which employs only two PTs and a fully integrated design. lt can achieve a peak VCR of1.78 and outputs power up to 8lmWwith a 91.8% peak PCE.

Low-cost metal (e.g., PCB trace) shunts can be used to make accurate current sensors (< 1 % gain error) [1-3]. However, their reported maximum operating temperature (85 circC) is not high enough for automotive applications, and at higher temperatures, shunt resistance may exhibit increased drift, especially at high current levels. This paper presents a metal-shunt-based current sensor with a wide temperature range and a stable on-chip reference current (I textREF) source for shunt self-calibration. By employing a continuous-time (CT) front-end, it achieves an input noise density of 14textnV/sqrttextHz while consuming only 280mu A, making it > 10times more energy efficient than prior art [1], [2], with comparable gain error (pm0.2%) over a wider current (pm 40A) and temperature (-40 circC to 125 circC) range.

In chopper amplifiers, the interaction between the input signal and the chopper clock can cause intermodulation distortion (IMD). This is due to amplifier delay, which causes signal transitions generated by the input chopper to arrive at the amplifier's output slightly later than the corresponding clock transitions of the output chopper. This causes large signal-dependent spikes in the final output, which can significantly degrade amplifier linearity, especially at input frequencies near even multiples of the chopping frequency FcH, which will cause IMD tones near DC. In [2-4], spread-spectrum clocks are used to convert such tones into noise-like signals. However, this increases the noise floor, without solving the underlying problem. Recently, it has been shown that such spikes can be eliminated by using the fill-in technique [1], in which two identical OTAs are chopped in quadrature, allowing a spike-free output to be generated by switching between their outputs in a ping-pong fashion.

This article presents a digital-input class-D amplifier (CDA) achieving high dynamic range (DR) by employing a chopped capacitive feedback network and a capacitive digital-to-analog converter (DAC). Compared with conventional resistive-feedback CDAs driven by resistive or current-steering DACs, the proposed architecture eliminates the noise from the DAC and feedback resistors. Intermodulation between the chopping, pulsewidth modulation (PWM), and DAC sampling frequency is analyzed to avoid negative impacts on the DR and linearity. Real-time dynamic element matching (RTDEM) is employed to address distortion due to mismatch in the DAC, while its intersymbol interference (ISI) is eliminated by deadbanding. The prototype, implemented in a 180-nm bipolar, CMOS, and DMOS (BCD) process, achieves 120.9 dB of DR and a peak total harmonic distortion plus noise (THD+N) of-111.2 dB. It can drive a maximum of 15/26 W into an 8-/4-Ω load with a peak efficiency of 90%/86%.

This article presents the design and implementation of a compact CMOS RC frequency reference. It consists of a frequency-locked loop (FLL) that locks the period of a voltage-controlled oscillator (VCO) to the time an RC network takes to charge to a reference voltage. Conventionally, an RC time constant with a near-zero temperature coefficient (TC) is realized by using a trimmed network of resistors with different TCs. In this work, such a network is used to realize a temperature-dependent reference voltage whose TC cancels that of a single-resistor RC time constant. Compared with the conventional approach, which requires resistors with TCs of opposite polarity, the proposed approach can be implemented with resistors with TCs of similar polarity, and so it can be implemented in most CMOS processes. To compensate for RC spread, a trimmed capacitor is used to adjust the nominal frequency. Two prototype chips were made, one based on p- /n-polysilicon resistors and other based on silicided/p-diffusion resistors. Fabricated in a standard 180-nm CMOS technology, the polysilicon-based prototype has an active area of 0.01 mm2 and an absolute inaccuracy of ±2800 ppm from -45 °C to 125 °C with a fixed TC-trim and a one-point frequency trim. After one week of accelerated aging at 150 °C, however, significant drift (5000 ppm) was observed. The diffusion-based prototype exhibits greater inaccuracy (±14 400 ppm) but much less drift (600 ppm).