This thesis presents the design of integrated interface circuits for inductive resonant wireless power transfer (WPT) systems, targeting implantable medical devices (IMDs). IMDs require compact, high-efficiency, and robust wireless power solutions capable of adapting to link and load variations. This thesis systematically develops three receiver and system architectures: voltage-mode (VM), hybrid voltage-/current-mode (V/CM), and resonant-current-mode (RCM), to improve power conversion efficiency (PCE), voltage conversion ratio (VCR), and adaptability over state-of-the-art designs.

This thesis focusses on improving the power efficiency of the front-ends used in wideband Continuous-Time Delta-Sigma Modulators (CTDSMs) (>100 MHz) with ultra-high linearity (<-100 dBc). The proposed front-end employs a passive RC Low-pass Filter (LPF) to suppress the high-frequency quantization noise at the output of the modulator’s feedback Digital-to-Analog Converter (DAC), thereby reducing the input swing in the front-end. The output of the LPF and the input signal are then summed by a low-noise Capacitively Coupled Instrumentation Amplifier (CCIA). This is followed by a pole-zero compensator, which ensures that the overall front-end behaves like an integrator. Simulations in a TSMC 28nm CMOS process indicate that a 5th-order CTDSM based on the proposed front-end will achieve better than -100 dBc THD and IM3, a peak SNDR of 74.1 dB over a 100 MHz bandwidth, while consuming only 45.4 mW of power. This is some 10% lower than that of prior work, and corresponds to a 167.5 dB Schreier Figure of Merit (FoM_S).

Cold-chain logistics demand precise temperature monitoring to ensure the safety and quality of perishable goods during transport. Conventional solutions rely on battery-powered temperature loggers, which contribute significantly to electronic waste due to limited reusability. This thesis addresses this environmental concern by contributing to the development of a fully batteryless, wireless temperature logger designed for long-duration cold-chain monitoring. Focusing on the sensing and data logging subsystem, this work presents the design and implementation of an ultra-low-power system capable of accurate temperature readout and multi-week data storage under strict energy constraints. The system integrates a microwatt-level temperature sensor, a power-optimized microcontroller, and energyefficient logging strategies to balance measurement accuracy, memory use, and power consumption. The final implementation is shown to have an idle power draw of <1μW and an energy use of 14μJ over the measurement and storage period, with a peak power of 411μW . The temperature measurements were found to be accurate within ±0.5°C . This accuracy and energy efficiency, demonstrates its potential as a sustainable alternative to traditional battery-powered loggers

Global cold-chain logistics demands compact, maintenance-free data loggers that document storage conditions without adding batteries or e-waste. This thesis presents the wireless transmission subsystem of a fully batteryless platform that harvests energy, stores data locally, and transmits it through an NFC link. After researching wireless standards, an ISO 15693/NFC-Forum Type-5 solution built around STMicroelectronics’ ST25DV64KC dynamic tag was selected for its I²C and RF dual-interface, non-volatile EEPROM and energy-harvesting capabilities.

The tag communicates with an ultra-low-power STM32U083 microcontroller over its I²C-bus to store the temperature data. Then, the data is transmitted to the reader via the connected antenna through the 13.56 MHz NFC electromagnetic field. At the same time, the antenna harvests residual energy from the reader, which is stored in an auxiliary capacitor. This stored energy provides a start-up power source for the energy harvesting system. Finally, a Python desktop script translates raw memory blocks into timestamped curves to visualise the logged temperature data.

Tests show that the NFC field of recent smartphones can provide sufficient energy for at least a full system duty-cycle in a single read. Additionally,the ST25DV64KC enables secure, wireless data retrieval , completing the architecture for integration into the project’s complete batteryless logger. Improvements can be made by optimising the auxiliary capacitor storage, antenna design, possible readout by NDEF and the UI by thorough software design.

This thesis presents the design and development of an energy harvesting system enabling a batteryless, wireless temperature-sensing data logger, intended for monitoring cargo conditions during maritime transport. The system harvests energy via inductive coupling, where a low-profile receiver coil captures power from an alternating magnetic field generated by a ceiling-mounted transmitter coil. This study specifically addresses key design considerations such as coil design, resonance-matching, Schottkydiode-based rectifification, robust voltage regulation by means of a buck-boost converter and a dual-capacitor energy storage scheme for reliable energy storage and voltage stability. The design overcomes core challenges in long-range wireless power transfer (WPT) including efficient energy extraction under low-power conditions, stable voltage regulation, and reliable start-up and operation within the constraints of a shipping container. The prototype achieves stable 2.1 V output from harvested energy alone, operating effectively at distances up to 1.4 m, while simulations confirm feasibile operation at the required 2.4 m range intended for its real-life application. The proposed solution achieves a self-sustaining, maintenance-free approach to temperature monitoring, enhancing cargo safety and contributing to the reduction of electronic and food waste. This system offers a scalable, adaptable, low-maintenance alternative to disposable battery-powered sensors, Improving sustainable cold-chain conditions monitoring and adhering to EU electromagnetic exposure limits.

This thesis presents a PNP-based temperature sensor that employs an energy-efficient current–voltage mirror (CVM) front-end. In contrast to prior PNP-based designs that rely on a low-noise but power-hungry bias amplifier, the proposed architecture replaces the amplifier with a symmetrically matched CVM, substantially reducing power consumption while preserving comparable noise performance. The PTAT voltage is generated using an emitter-area ratio rather than a current ratio, further improving energy efficiency. To suppress mismatch, flicker noise, and offset-related errors, several dynamic techniques—including bitstream-controlled DEM, chopping, and resistor-ratio calibration—are incorporated into the system. Simulated in a 0.18-μm CMOS process, the design achieves a resolution FoM of 0.558 pJ·K2, with a resolution of 1.97 mK at a 38.4 ms conversion time. It attains an inaccuracy of 0.1◦C (3σ) over the −55◦C to 125◦C temperature range after one-point trimming, while consuming only 3.75 ¯W. These results demonstrate that CVM-biased front-ends provide a promising direction for next-generation ultralow-power PNP temperature sensors.

In this thesis, a low-power, sub-1V, high-accuracy capacitively-biased-diode (CBD)-based temperature sensor with excellent power supply sensitivity (PSS) in a 65 nm LP process is proposed. The sensor consists of two main parts: a CBD front-end and a Delta-Sigma Modulator (DSM). The CBD front-end discharges pre-charged capacitors via diode-connected BJTs to generate accurate proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) voltages. The ratio of these voltages is then digitized by a second-order switched-capacitor DSM, which employs energy-efficient inverter-based amplifiers capable of operating from a sub-1V supply.

After a one-point temperature calibration, the BJT-based sensor achieves a simulated inaccuracy of ±0.2 °C (3σ) over the temperature range from −55 °C to 125 °C. Over the entire temperature range, the BJT-based sensor achieves a PSS of 0.05 °C/V from 0.9 V to 1.4 V. Compared to previous CBD-based temperature sensors, this design achieves 10× better PSS.

Integrated temperature sensors are widely used in various applications, including thermal monitoring, medical devices, and voltage/frequency references. An emerging class of temperature sensors operates by measuring the thermal diffusivity (TD) of silicon. This can be done by measuring the time it takes for heat to diffuse between a heater and a relative temperature sensor, both implemented in a silicon substrate. The key advantage of such TD-based sensors is that their accuracy improves linearly with lithographic precision.

Increasing the length of the heat path and/or moving to a more advanced technology node will enhance measurement accuracy. However, since silicon is an excellent heat conductor, the output of such sensors is at the millivolt level, which makes the design of accurate readout circuitry quite challenging.

In this work, an accurate readout circuit was designed for TD-based sensors realized in a 65nm process. It consists of a low-noise pre-amplifier, followed by a Sigma-Delta ADC. Based on simulation results, the designed circuit achieves a 23 mK (3σ) inaccuracy at 27◦C, which is negligible compared to the expected inaccuracy of the TD-based sensors.

This thesis presents the design, circuit implementation, and measurement results of energy-efficient interface circuits for piezoelectric energy harvesting (PEH).

Chapter 1 introduces the background and motivation for this work. It begins by discussing various application scenarios for wireless sensors and emphasizes the critical need for a sustainable power supply to ensure their long-term operation. Energy harvesting systems are identified as a promising alternative to traditional batteries, with piezoelectric energy harvesting standing out as an ideal solution due to the ubiquitous presence of ambient vibrations in the environment. Since efficient energy conversion requires dedicated interface circuits, the chapter reviews typical circuit architectures and highlights three main challenges in the state-of-the-art: the trade-off between system size and rectifier efficiency, the sensitivity and complexity of maximum power point tracking (MPPT) algorithms, and low end-to-end efficiency due to cumulative energy losses in cascaded architectures.

Chapter 2 provides a comprehensive review of existing interface circuits commonly used in PEH systems. To enhance the output power efficiency of rectifiers, various active rectification techniques have been proposed, such as Synchronized Switch Harvesting on Inductor (SSHI) and Synchronized Switch Harvesting on Capacitor (SSHC). However, SSHI requires bulky inductors, while SSHC depends on multiple dedicated flying capacitors, increasing the system’s overall volume. The chapter also introduces two widely used MPPT techniques—Fractional Open-Circuit Voltage (FOCV) and Perturb and Observe (P&O). Both approaches have their respective drawbacks: FOCV requires open-circuit voltage sampling and flipping efficiency calibration, which results in discontinuous tracking and energy loss; P&O, on the other hand, relies on complex circuitry and consumes significant power. Finally, the chapter analyzes the issue of cascaded energy losses in current system architectures, which leads to relatively low end-to-end efficiencies, typically ranging from 50% to 80%.

Chapter 3 addresses the challenge of minimizing rectifier volume without compromising efficiency by proposing a synchronized switch harvesting rectifier that utilizes reusable storage capacitors. In this design, three capacitors are shared to function both as energy storage elements and as temporary flying capacitors during the energy harvesting and piezoelectric transducer (PT) voltage flipping phases. These capacitors are dynamically reconfigured into nine connection states during the flipping period, effectively replicating the functionality of conventional SSHC flying capacitors. This sharing and reconfiguration technique significantly reduces system size. Measurement results show a PT voltage flipping efficiency of 78%, demonstrating the design’s potential for compact, high-efficiency energy harvesting applications.

Chapter 4 proposes a duty-cycle-based (DCB) MPPT algorithm to overcome the limitations of the FOCV and P&O techniques. The DCB algorithm establishes a direct relationship between the rectifier’s on-off duty cycle and its maximum power point (MPP). Mathematical analysis shows that maintaining a 50% duty cycle allows the system to operate at its MPP. Unlike FOCV, this approach eliminates the need for open-circuit voltage sampling and flipping efficiency calibration. It also avoids the complex power computations and hardware overhead associated with P&O. In addition to its simplicity, the DCB method offers robust tracking performance. Experimental results demonstrate a peak MPPT efficiency of up to 98%, with an average tracking efficiency of 94%.

Chapter 5 presents a single-stage bias-flip rectifier to address the issue of cascaded energy loss in conventional PEH system architectures. This design transfers energy directly from the PT to the output capacitor, reducing intermediate losses. By fixing the rectifier’s on-off duty cycle at 50% to achieve MPPT, the need for a separate rectified capacitor is eliminated, resulting in a shorter startup time and faster MPPT response. Experimental results show an end-to-end efficiency of up to 92.5%, with energy extraction performance improved by a factor of 9.3× compared to a full-bridge rectifier (FBR).

Chapter 6 summarizes the main findings of the thesis and compares the proposed designs in Chapters 3, 4, and 5 with the current state-of-the-art. It also outlines potential directions for future work, including 1) the development of a fully capacitive rectifier with output regulation, 2) MPPT strategies under non-ideal sinusoidal excitation conditions, and 3) power limit analysis and corresponding optimization techniques.

This thesis presents the design and realization of high-performance hybrid contactless current sensors implemented in standard CMOS technology. The research addresses a key challenge in contactless current measurement: achieving simultaneously wide bandwidth, high resolution, and low drift while maintaining low cost. Conventional contactless sensing elements such as Hall plates and pick-up coils each exhibit complementary strengths—Hall plates offer DC sensing but limited signal-to-noise ratio (SNR) at high frequencies, whereas pick-up coils provide high-frequency sensitivity but cannot detect DC. This work proposes and demonstrates hybrid CMOS sensors that combine both elements in a single architecture, exploiting their advantages to obtain a flat frequency response from DC to several MHz.

Internet-of-Things (IoT) applications require nanowatt (nW) power references that are robust to process, voltage, and temperature (PVT) variations. This thesis presents the design of ultra-low-power (ULP) sub-10nW always-on blocks in GlobalFoundries 22nm (GF22nm) technology, including a Proportional to Absolute Temperature (PTAT) current reference, a bandgap reference, and a Low Dropout Regulator (LDO). These references are optimized to operate over the full automotive temperature range while consuming only 1nA of current per branch.

Given the high cost of GF22nm technology, achieving area efficiency is a critical aspect of this research. To address this, the design incorporates area-efficient components such as switched capacitors and duty-cycled resistors. The PTAT block achieves a line sensitivity of 2%/V and 5% spread (σ/μ) at 27°C consuming 4nW by utilizing MOSFETs in weak inversion and operates with an 800mV supply voltage while occupying a silicon area of 0.001mm². The bandgap reference is supplied from a battery with an end-of-life (EOL) voltage of 900mV. It achieves a maximum temperature coefficient (TC) of 140.6ppm/°C and a line sensitivity of 0.56%/V at 27°C with a supply range from 900mV to 1.98V. Without resistor trimming, the reference voltage spread due to process and mismatch variations is reduced to 2.9% (σ/μ) by using BJTs. The bandgap reference occupies a silicon area of 0.021mm² using duty-cycled resistors and has a nominal power consumption of 7.6nW. This voltage is used as the reference voltage for an LDO with unity-gain feedback to prevent multiplication of the reference voltage noise. The LDO maintains an output voltage line sensitivity of less than 1%/V with battery voltage variations from 900mV to 1.98V and load currents ranging from 100nA to 1µA.

CMOS Hall sensors consist of current-biased n-well plates that output magnetic-field dependent voltages. Offsets due to n-well inhomogeneity can then be suppressed by the spinning-current technique, which involves periodically rotating the direction of the biasing current and averaging the resulting output voltages. However, its effectiveness is limited by the JFET effect, which refers to the formation of a depletion region between the n-well and the p-type substrate due to the voltage drop across the n-well. This depletion region modulates the n-well resistance, and so is also a source of residual offset.

In this work, a CMOS Hall sensor is reported which employs voltage biasing and reads out the short-circuit Hall current. Compared to current biasing, this stabilizes the voltage drop across the n-well and significantly reduces the offset due to the JFET effect. Implemented in a standard 180nm CMOS process, the resulting sensor achieves a 3σ offset of 1.1μT with a noise floor of 60nT/√Hz. Compared to the state-of-the-art, these results represent a 3x reduction in offset, and a 5x improvement in resolution.

This thesis describes the implementation of a phase-domain readout system for a thermal-diffusivity (TD) based temperature sensor. Such sensors measure the phase shift of an electro-thermal filter (ETF), which exhibits a near-linear dependency on absolute temperature. The phase shift is measured by a phase-domain delta-sigma modulator (PD-DSM). Although ETFs can be very accurate, their readout circuitry often constrains overall performance. A notable concern is their offset, which is usually much larger than the ETF’s output signal and may cause the PD-DSM to clip. In this work, this issue is addressed by a hybrid offset-reduction strategy. The PD-DSM itself is designed to achieve a temperature inaccuracy of 0.04°C.
The design was fabricated using TSMC 180nm CMOS technology. Due to a design error, the PD-DSM did not achieve the targeted accuracy. Nonetheless, the hybrid offset cancellation scheme works as intended, demonstrating efficacy by effectively mitigating residual offset to sub-µV levels across temperature ranges extending up to 180°C.

In this thesis, a low-power, high-accuracy BJT-based temperature sensor is proposed, which consists of two main parts: a BJT-based dual-mode front-end (DMFE) and a tracking Delta-Sigma-Modulator (DSM). The front-end employs vertical PNP transistors, which, compared to NPNs, exhibit fewer non-idealities when biased at nA-level currents. The proposed DMFE generates accurate proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) voltages, while only consuming half the power of a conventional front-end. The temperature dependent ratio of these voltages is then digitized by an energy-efficient tracking DSM. The prototype sensor was fabricated in a 0.18µm CMOS process and has an active area of 0.228mm2. Measurement results show that the sensor achieves an inaccuracy of ±0.15°C (3σ) over the industrial temperature range (-45°C to 85°C) after 1-point temperature calibration, which corresponds to a relative inaccuracy of 0.3%. It also achieves a 32mK resolution in 100ms, while consuming only 130nW. Its low power consumption, accuracy, and resolution make it suitable for IoT applications.

Temperature greatly affects the performance of integrated circuits, and so temperature sensors are often necessary to ensure reliable operation and stable performance. The goal of the work described in this thesis is to realize a temperature sensor in CMOS technology that can be produced at low cost. In the first step, a temperature sensor is developed that, unlike its predecessors, does not require individual batch calibration, thus significantly reducing calibration costs. In the second step, low-cost calibration methods are developed to calibrate the sensor at two different temperatures: room temperature and an elevated temperature created by an on-chip heater. These calibration methods are used to correct the shifts in the sensor's output caused by the mechanical stress of plastic packaging or to maintain the sensor's accuracy over a wide temperature range. In the final step, additional functionality is added to the sensor to measure external capacitances and voltages. This is achieved by reusing the circuitry of the temperature sensor, thereby making a cost-effective use of its area.

This thesis describes the analysis, design, prototype implementation, and measurement results of high-performance Class-D amplifiers (CDAs) for audio applications.

Advanced Systems-on-Chip (SoCs) exhibit significant self-heating and require thermal management to prevent overheating. Sensors for this application should be not only small so that they can be placed ubiquitously, but they should also achieve moderate accuracy and resolution within 1 ms so that the die temperature can be monitored with approximately 1°C of measurement error. BJTs are the traditional elements that are used to sense temperature, but they require large headroom and are difficult to miniaturize. Thermal diffusivity relies solely on lithography for its accuracy and is easy to miniaturize, but it requires a significant amount of power (a few mWs) to generate the local heat pulses that it uses to measure temperature. MOS-based temperature sensors do not require the headroom that BJT-based sensors do, but they do require a large area to minimize the effect of aging and drift. Resistors achieve superior energy efficiency, moderate accuracy (enough for thermal management), and have no headroom requirements. However, at the beginning of this work, these types of sensors were not yet miniaturized.

This thesis describes the design, implementation, and characterization of integrated RC frequency references. The primary focus of the work is a frequency-locked loop (FLL) architecture, realized in standard CMOS, that digitizes the phase shift of an integrated RC filter, processes the results in the digital domain, and uses it to control an output frequency to maintain its accuracy over temperature variations.....

This thesis describes the development of high-performance Class-D audio amplifiers, outlining their significance in modern audio systems. The primary aim is to reduce the system cost and size associated around Class-D amplifiers by minimizing the use of off-chip components, while ensuring high performance and audio fidelity.

Chapter 1 introduces audio amplifiers as integrated circuits, highlighting their role in amplifying electrical signals to drive loudspeakers in various applications. It outlines the key factors influencing amplifier design, including system cost and size, output power, efficiency, electromagnetic interference (EMI), and audio fidelity. The chapter briefly discusses two major classes of amplifiers- Class-AB and Class-D amplifiers (CDAs), particularly emphasizing the latter for high efficiency benefits on account of the switching output stage. Additionally, it introduces the two types of speakers that the amplifiers in this work are optimized to drive, the conventional electrodynamic speaker and the increasingly popular piezoelectric speaker. The discussion includes the advantages and disadvantages of each speaker type and how their electrical impedances impact amplifier design.

Chapter 2 delves into the architectural and circuit techniques used in modern CDAs, comparing different output stage topologies and modulation schemes, and their impact on high-frequency PWM energy and ripple current — key measures of the amplifier’s EMI performance. It introduces conventional AD / BD PWM modulation schemes, highlighting their high frequency PWM characteristics from DM and CM perspectives, before exploring more complicated multi-level and multi-phase architectures that aim to reduce the ripple content and EMI. The trade-offs between these modulation schemes in terms of EMI performance and component requirements are examined. It discusses the benefits of increasing the PWM switching frequency above the AM band ( 1.7MHz), which then allows for smaller and cheaper LC filters. Pulse-density modulation (PDM) using a 1-bit delta-sigma modulator (ΔΣM) is covered, emphasizing its benefits in terms of linearity and challenges related to wideband quantization noise and EMI. Lastly, the chapter also addresses the adaptability of CDAs for driving various speaker loads, particularly newer piezoelectric speakers, and discusses innovative techniques for damping LC resonance without external resistors, significantly reducing power consumption and system cost.

Chapter 3 outlines the development of a 28WCDA for automotive applications, employing a hybrid multibit ΔΣM-PWM scheme to achieve high linearity and low EMI in the AM band. The design features a fully-differential 3rd order loop filter, a multilevel non-uniform quantizer, and an H-bridge output stage that operates at a switching frequency above the AM band. This hybrid modulation technique addresses the limitations of 1-bit delta-sigma modulation, and significantly reducing out-of-band emissions while maintaining high linearity across a broad output power range thanks to the high-gain loop filter. The digital and analog circuits in this design, including the loop filter integrators and quantizer, are designed with low-voltage devices to ensure area and power efficiency. In contrast, the high-power output stage and driving circuits are built with more robust high-voltage devices. This prototype amplifier meets the stringent CISPR-25 EMI standards within the AM band using a relaxed LC filter, while also achieving high linearity, dynamic range, and supply rejection. Chapter 4 introduces a CDA that incorporates a dual voltage/current feedback (VFB/ CFB) topology, specifically designed to drive capacitive piezoelectric speaker loads without the need for external damping resistors. This dual-loop structure effectively mimics a series resistor in an LCR network, allowing for resistor-less LC resonance damping, thereby reducing cost, size, and power consumption. Load current sensing, used in the CFB path, is implemented using purely low-side on-chip sense resistors, thereby avoiding high-frequency switching issues and simplifying the readout network. This low-side sensing is feasible due to the push-pull modulation scheme, which is advantageous for a low-power design. Techniques such as CFB filtering and chopping are employed to reduce non-idealities like noise and non-linearity in the feedback paths. The prototype, fabricated in a 180 nm BCD process, can drive a 4 μF load with a peak current of 4.4 A and achieves an idle power consumption of 122 mW. Measurement results confirm the system’s efficacy in damping LC resonance and maintaining high performance, with significant power savings compared to traditional designs using external resistors.

Chapter 5 builds upon the dual feedback architecture introduced in Chapter 4 by incorporating a quadrature chopping scheme to further enhance the linearity and noise performance of Class-D amplifiers. This technique addresses timing skew issues between low-voltage input choppers and high-voltage output choppers, which can degrade signal linearity and increase noise. The quadrature chopping scheme dynamically matches the timing of the choppers, resulting in significant improvements in large-signal total harmonic distortion (THD) and a reduction in noise foldback into the audio band. The chapter presents measurement results that demonstrate the extension in the linear output of the amplifier to close to 95% the full-scale.

Chapter 6 concludes the thesis by summarizing the key findings and contributions of the research. It highlights the original contributions, including the hybrid PWM-DSM modulation scheme, the dual feedback topology for resistor-less damping of capacitive piezoelectric speaker loads, and the quadrature chopping scheme for further improved linearity and noise performance. The chapter also discusses potential future research directions, such as further optimization of EMI performance through advanced modulation techniques, improved current sensing methods, and enhanced feedback accuracy.