This thesis focusses on improving the power efficiency of the front-ends used in wideband Continuous-Time Delta-Sigma Modulators (CTDSMs) (>100 MHz) with ultra-high linearity (<-100 dBc). The proposed front-end employs a passive RC Low-pass Filter (LPF) to suppress the high-frequency quantization noise at the output of the modulator’s feedback Digital-to-Analog Converter (DAC), thereby reducing the input swing in the front-end. The output of the LPF and the input signal are then summed by a low-noise Capacitively Coupled Instrumentation Amplifier (CCIA). This is followed by a pole-zero compensator, which ensures that the overall front-end behaves like an integrator. Simulations in a TSMC 28nm CMOS process indicate that a 5th-order CTDSM based on the proposed front-end will achieve better than -100 dBc THD and IM3, a peak SNDR of 74.1 dB over a 100 MHz bandwidth, while consuming only 45.4 mW of power. This is some 10% lower than that of prior work, and corresponds to a 167.5 dB Schreier Figure of Merit (FoM_S).