This letter presents an aging-robust 32MHz RC frequency reference based on a frequency-locked-loop (FLL). With a temperature compensation scheme that combines BJTs and aging-robust diffusion resistors, the FLL achieves ±1550ppm inaccuracy from -40°C to 125°C after batch calibration and a low-cost 1-point trim, which increases to ±2350ppm after accelerated aging. Due to the extensive use of dynamic error-correction techniques, the FLL also achieves a state-of-the-art Allan deviation floor of 0.4ppm.

This article presents a photovoltaic energy harvester (PVEH) that achieves high maximum power point tracking (MPPT) efficiency and power conversion efficiency across a 100 000× input power dynamic range (DR) (from 10 µW to 1 W). Wide-dynamic-range operation is challenging due to the inherent tradeoff between MPPT accuracy and controller power consumption. To address this, an adaptive power-scalable MPPT scheme is proposed, employing a direct power-to-digital converter (PDC) that eliminates the need for current sensing, analog multipliers, or lookup tables (LUTs). The PDC utilizes an equivalent power comparison technique, minimizing its power consumption. The MPPT controller autonomously scales its power, consuming minimal energy in low-irradiation conditions while maintaining high tracking accuracy and speed in high-irradiation conditions. Furthermore, a multiple-counting technique mitigates comparator noise and settling errors. Implemented in a 180-nm CMOS process, the harvester achieves a peak MPPT efficiency of 99.9% and maintains >98% across the entire range, representing a 10× improvement in DR over prior art. It also achieves a competitive power conversion efficiency of >82% (peak of 92%) over the same DR.

Compute-in-memory (CIM) accelerators for spiking neural networks (SNNs) are promising solutions to enable μs-level inference latency and ultra-low energy in edge vision applications. Yet, their current lack of flexibility at both the circuit and system levels prevents their deployment in a wide range of real-life scenarios. In this work, we propose FlexSpIM, a novel digital CIM macro that supports arbitrary operand resolution and shape within a unified CIM storage for weights and membrane potentials. These circuit-level techniques enable a hybrid weight- and output-stationary dataflow at the system level to maximize operand reuse, thereby minimizing costly on- and off-chip data movements during the SNN execution. Measurement results of a fabricated FlexSpIM prototype in 40-nm CMOS demonstrate a 2× increase in 1-bit-normalized energy efficiency compared to prior fixed-precision digital CIM-based SNNs, while providing resolution reconfiguration with bitwise granularity. Our approach can save up to 90% energy in large-scale systems, while reaching a state-of-the-art classification accuracy of 95.8% on the IBM DVS gesture dataset.

RC-based frequency references [1-6] are widely used for clock generation in SoCs since they are compact, low power, and can achieve medium frequency accuracy. Designs based on low-TC poly resistors can achieve inaccuracies of a few 100 ppm[1-5], but this is dwarfed by their drift, which can be as large as 5000 ppm after accelerated aging [5-6]. Although designs based on via-metal [4] or diffusion [6] resistors exhibit significantly lower drift, in the order of several 100 ppm, their larger TCs mean that a 2-point trim is required to achieve inaccuracies of several 100 ppm. This paper presents an aging-robust 32 MHz RC frequency reference based on diffusion resistors and a BJT-based temperature compensation scheme. After a low-cost 1-point trim, it achieves ± 1550ppm inaccuracy from -40 C to 125 C, which increases to ± 2350ppm after accelerated aging. Due to the extensive use of dynamic error-correction techniques, it also achieves an Allan deviation floor of 0.4 ppm, corresponding to state-of-the-art short-term stability.

This article describes the design and implementation of a compact CMOS RC frequency reference based on N-type diffusion (N-diff) resistors and metal-insulator-metal (MIM) capacitors. It consists of a frequency-locked loop (FLL) that locks the period of a voltage-controlled oscillator (VCO) to the time it takes a current source to charge a capacitor to a reference voltage. Conventionally, the temperature compensation of such FLLs involves the use of resistors with different temperature dependencies. In this work, however, this is done by using two bipolar junction transistor (BJT)-based current sources with different temperature dependencies to charge a MIM capacitor and generate a reference voltage across an N-diff resistor, respectively. Implemented in a standard 180-nm technology, the resulting frequency reference achieves small size (0.028 mm²), moderate inaccuracy (±900 ppm) from -40 ^°C to 125 ^°C, and low drift (±1600 ppm) after accelerated aging. The versatility of the proposed temperature compensation scheme is validated by replacing the N-diff resistor with a P-poly resistor. However, the latter exhibits greater inaccuracy (+2000/-2500 ppm) and more drift (-2600/-8100 ppm) after accelerated aging.

This paper presents a high-accuracy, low-drift 16 MHz RC frequency reference. It is based on a Wien bridge filter that incorporates silicided n-poly resistors and MIM capacitors, whose temperature coefficient is compensated by a PNP-based temperature sensor. After a 2-point trim, it achieves ± 350 ppm inaccuracy from -45°C to 85° C, which increases to only ± 450 ppm after accelerated aging. This represents competitive accuracy and state-of-the-art stability for RC-based frequency references, approaching that of their LC-based counterparts while dissipating lower power and occupying less area.

This paper presents a photovoltaic energy harvesting (PVEH) system achieving both high Maximum Power Point Tracking (MPPT) efficiency (η _MPPT) and power conversion efficiency (η _CONV) across a wide input power dynamic range (DR), employing a direct input power-to-digital converter (PDC) and an adaptive power-scalable MPPT scheme. The proposed PVEH achieves >98% (with a peak of 99.9%) η _MPPT across a 100,000 × DR (10 μ W to 1 W), representing a 10 × improvement over the state-of-the-art, as well as a competitive η _CONV of >82% (with a peak of 92%) across the same DR.

This article presents a compact sub-1-V bipolar junction transistor (BJT)-based temperature sensor for thermal management applications. To operate from a sub-1-V supply, two capacitors are first pre-charged to a supply-independent initial voltage (> 1 V) by regulated charge pumps (RCPs) and then discharged through two diode-connected BJTs. By using different discharge times, proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) voltages can be generated. These are then read out by an area-and energy-efficient charge-balancing ΔΣ modulator to generate a digital representation of temperature. To reduce its noise, the modulator's first inverter-based integrator employs both chopping and auto-zeroing. Fabricated in a standard 22-nm bulk CMOS process, the sensor occupies 0.01 mm² and consumes 2.9 μW from a 0.8-V supply. It achieves a 1-point trimmed inaccuracy of ± 0.4 °C (3σ) from -40 °C to 125 °C, which is the best reported in sub-65-nm CMOS. It also achieves high energy efficiency, resulting in a resolution figure of merit (FoM) of 0.41

This paper presents a direct conversion transceiver intended for use in a microfluidic NMR flowmeter. It consists of an H-bridge power amplifier, which drives a hand-wound milimeter-sized coil with RF signals, and a direct conversion receiver, which amplifies the NMR signals picked up by the coil, and then digitizes them with an asynchronous 8 bit SAR ADC sampling at 70 MHz. Fabricated in a 65 nm CMOS technology, the receiver achieves a noise spectral density of 1 nV/sqrt(Hz) at 21 MHz, while dissipating only 36 mW. A microfluidic flowmeter based on the transceiver and a handheld 0.5 T permanent magnet can measure flow rates up to 96 ml/h in a 0.8 mm inner-diameter channel with pm 1.3 % full-scale error. To the authors' best knowledge, this is the first reported portable NMR flowmeter.

Bias-flip rectifiers are commonly employed for piezoelectric energy harvesting (PEH). This article proposes a synchronized switch harvesting on an inductor (SSHI) rectifier with a duty-cycle-based (DCB) maximum power point tracking (MPPT) algorithm. The proposed DCB MPPT algorithm is based on the mathematically derived relation between the MPPT efficiency and the duty cycle of the bridge rectifier. The resulting equation shows that the MPPT efficiency only depends on the rectifier duty cycle, and is independent of any other system variables, such as voltage bias-flipping efficiency, the open-circuit voltage from the harvester, vibration frequency, etc. As a result, MPPT can be achieved by regulating the duty cycle, simplifying circuit implementation, and achieving self-regulating and continuous MPPT. This design was fabricated in a 180-nm BCD process. The measured results show 98% peak MPPT efficiency and up to 738% output power enhancement.

Advances in CMOS technologies and circuit techniques have led to the development of continuous-time delta-sigma modulators (CTΔ Σ Ms) that sample at gigahertz (GHz) frequencies and achieve high linearity [-100 dBc and >120 dBFS spurious-free dynamic ranges (SFDRs)] in wide bandwidths (>100 MHz). However, at low frequencies (≤ 10 MHz), their performance is limited by the 1/f noise generated by the near-minimum size devices used in their wide-bandwidth input stages. This, in turn, limits their use in radio receivers intended to cover both the AM and FM bands. In this work, a multi-path multi-frequency chopping scheme is proposed to suppress 1/f noise, while preserving interferer robustness, thermal noise levels, and linearity. Implemented in a CTΔ Σ analog-to-digital converter (ADC) sampling at 6 GHz, it achieves a 22× reduction in 1/f noise, as well as 122-dBFS SFDR and -98.3-dBc THD in a 120-MHz BW.

This article presents a 14-bit fully dynamic sensor interface that consists of a switched-capacitor (SC) ΔΣ modulator and a dynamic bandgap reference (BGR). The BGR is implemented by summing the proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) outputs of two PNP-based capacitive DACs. At the sampling rate, the DAC capacitors are pre-charged to the supply and then discharged for a fixed period via PNPs, thus biasing them and simultaneously sampling their base-emitter voltages. By using the modulator's first integrator to sum the DAC outputs, a dynamic BGR can be realized, which does not need additional reference buffers or decoupling capacitors. To make the system fully dynamic, the modulator itself is based on capacitively biased (CB) floating inverter amplifiers (FIAs). Implemented in a standard 130-nm CMOS process, the sensor interface occupies an area of 0.2 mm². It achieves an SNDR of > 84.5 dB over a scalable bandwidth (BW) ranging from 98 Hz to 5.9 kHz while consuming 1.7-50.8 μW. Furthermore, by employing a time-domain temperature-compensation scheme, it achieves a batch-trimmed gain error of ± 0.26% from -40°C to 125 °C.

This article presents a CMOS temperature sensor that achieves both state-of-the-art energy efficiency and accuracy. An NPN-based front end uses two resistors to efficiently generate a PTAT and CTAT current, whose ratio is then digitized by a continuous-time (CT) Δ Σ -modulator. A β-compensation technique is used to mitigate base current errors associated with the NPN's finite β. Component mismatch and 1/f noise are mitigated by applying chopping and dynamic element matching (DEM), while the spread in V_BE and the ratio of the two resistors are digitally trimmed at room temperature (RT). Fabricated in a 0.18-μ m CMOS process, the sensor draws 2.5μ A from a supply voltage ranging from 1.4 to 2.2 V. Measurements on 40 samples show that it achieves an inaccuracy of ± 0.1° C (3Σ ) from - 55° C to 125° C. Furthermore, it is both highly energy efficient, with a resolution figure of merit (FoM) of 200fJċK² , as well as very compact, occupying only 0.07 mm2.

This article describes a PNP-based temperature sensor that achieves both high energy efficiency and accuracy. Two resistors convert the CTAT and PTAT voltages generated by a PNP-based front-end into two currents whose ratio is then digitized by a continuous-time (CT) Δ Σ -modulator. Chopping and dynamic-element-matching (DEM) are used to mitigate the effects of component mismatch and 1/f noise, while the spread in V _BE and in the ratio of the two resistors is digitally trimmed at room temperature (RT). Fabricated in a 0.18μ m CMOS process, the sensor occupies 0.12 mm ², and draws 9.5μ A from a supply voltage ranging from 1.7 to 2.2 V. Measurements on 40 samples from one batch show that it achieves an inaccuracy of ± 0.1° C (3σ) from -55° C to 125° C, and a commensurate supply sensitivity of only 0.01° C/V. Furthermore, it achieves high energy efficiency, with a resolution Figure of Merit (FoM) of 0.85

This brief presents a capacitively-biased CMOS voltage reference, which can operate from a sub-1V supply while achieving a low temperature coefficient (TC) and a competitive power-supply rejection ratio (PSRR). The reference voltage is generated by a capacitive bias circuit that provides a well-defined proportional-to-absolute-temperature (PTAT) bias current for a ΔVth type reference that consists of two stacked MOSFETs with different threshold voltages. The generated output voltage is sampled by an auto-zeroed (AZ) buffer, which can drive capacitive loads up to 2 nF. Fabricated in a 65 nm CMOS process, the prototype voltage reference occupies 0.058 mm2, including the AZ buffer and an on-chip timing generator. It outputs a reference voltage of 204.1 mV with a minimum supply voltage of 0.7 V. It achieves a TC of 18 ppm/° C from -40 ° C to 85 ° C and a PSRR of -75 dB at 100 Hz with only 200 μV ripple.

A single-stage dual-output regulating voltage doubler (DOVD) is proposed for biomedical wireless power transfer (WPT) systems. Derived from the full-wave voltage doubler (VD) topology, it achieves ac-to-dc rectification and dual-output voltage regulation in a single stage by using only two power transistors. The DOVD's inherent voltage conversion ratio (VCR) of 2 enhances the overall voltage gain of a WPT system, thus extending the transfer range against varying link conditions. To eliminate cross-regulation between the two outputs and provide fast load-transient responses, a parallel pulse-frequency modulation (PPFM) controller is proposed. In addition, a digital-tuning adaptive delay compensation technique with fast error-variation responses is proposed to achieve soft-switching in the power stage. Implemented in a 180-nm Bipolar-CMOS-DMOS (BCD) technology and operating at 6.78 MHz, the proposed DOVD achieves dual regulated outputs at 1.8 and 3.3 V, a VCR of up to 1.875, and a power conversion efficiency (PCE) of up to 92.95% over an output power range of 2.6-90.5 mW. It also achieves instant load-transient responses and unnoticeable cross-regulation during 25× load transients at both outputs.

Magnetic current sensors are widely used in applications where galvanic isolation and wide bandwidth (BW) are desired, such as in switched-mode power supplies and motor drivers. By using Hall plates for low frequencies and pick-up coils for high frequencies, hybrid magnetic sensors can achieve high resolution (tens of textmA) over a wide frequency range (up to 15MHz) [1]-[3]. However, previous designs exhibit either poor gain flatness over frequency or limited energy efficiency. This work presents a hybrid magnetic current sensor that textachievespm 1. 1% gain flatness, which is 3times better than prior art [1]-[3]. Its energy efficiency is also 11times better than the state-of-the-art [1], [4], [5].

This article presents a hybrid magnetic current sensor for galvanically isolated measurements. It consists of a CMOS chip that senses the magnetic field generated by current flowing through a lead-frame-based current rail. Hall plates and coils are used to sense low-frequency (dc to 10 kHz) and high-frequency (10 kHz to 5 MHz) magnetic fields, respectively. With the help of on- chip calibration coils, the biasing current of the Hall plates is trimmed to match the sensitivity of the Hall and coil signal paths. The sensitivity drift of the coil path with temperature is compensated by using temperature-dependent gain-setting resistors, while the drift of the Hall path is compensated by biasing the Hall plates with a proportional- to-absolute-temperature (PTAT) current. The resulting sensitivity drift is less than 9% from-40 °C to 80 °C. The offset of the Hall plates is reduced by the current spinning technique, and the resulting ripple is suppressed by a multiplexed ripple-reduction loop (MMRL). Fabricated in a standard 0.18-μm CMOS process, the current sensor occupies 4.6 mm2 and draws 7.8 mA from a 1.8-V supply. It achieves a gain variation of only ±2% in a 5-MHz BW. It also achieves high energy efficiency, with an figure of merit (FoM) of 1.6 fW/Hz.