A 120-MHz BW, 122-dBFS SFDR CT ΔΣ ADC With a Multi-Path Multi-Frequency Chopping Scheme

Journal article (2024)

Authors

L.S. Javvaji Electronic Instrumentation - EEMCS
M. Bolatkale NXP Semiconductors
Shagun Bajoria NXP Semiconductors
Robert Rutten NXP Semiconductors
Bert Oude Essink NXP Semiconductors
Koen Beijens NXP Semiconductors
K.A.A. Makinwa Microelectronics
L.J. Breems NXP Semiconductors
Research Group
Electronic Instrumentation (EEMCS) (TU Delft)
Analog-to-digital converter (ADC) Continuous time (CT) Multi-path chopping Wideband receiver
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Published Date

2024

Language

English

Reuse Rights

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronic Instrumentation

Abstract

Advances in CMOS technologies and circuit techniques have led to the development of continuous-time delta-sigma modulators (CTΔ Σ Ms) that sample at gigahertz (GHz) frequencies and achieve high linearity [-100 dBc and >120 dBFS spurious-free dynamic ranges (SFDRs)] in wide bandwidths (>100 MHz). However, at low frequencies (≤ 10 MHz), their performance is limited by the 1/f noise generated by the near-minimum size devices used in their wide-bandwidth input stages. This, in turn, limits their use in radio receivers intended to cover both the AM and FM bands. In this work, a multi-path multi-frequency chopping scheme is proposed to suppress 1/f noise, while preserving interferer robustness, thermal noise levels, and linearity. Implemented in a CTΔ Σ analog-to-digital converter (ADC) sampling at 6 GHz, it achieves a 22× reduction in 1/f noise, as well as 122-dBFS SFDR and -98.3-dBc THD in a 120-MHz BW.