A Sub-1-V Capacitively-Biased Voltage Reference with an Auto-Zeroed Buffer and a TC of 18-ppm/° C
Heungsik Eum (Yonsei University)
Kofi A. A. Kofi (TU Delft - Microelectronics)
Inhee Lee (University of Pittsburgh)
Youngcheol Chae (Yonsei University)
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Abstract
This brief presents a capacitively-biased CMOS voltage reference, which can operate from a sub-1V supply while achieving a low temperature coefficient (TC) and a competitive power-supply rejection ratio (PSRR). The reference voltage is generated by a capacitive bias circuit that provides a well-defined proportional-to-absolute-temperature (PTAT) bias current for a ΔVth type reference that consists of two stacked MOSFETs with different threshold voltages. The generated output voltage is sampled by an auto-zeroed (AZ) buffer, which can drive capacitive loads up to 2 nF. Fabricated in a 65 nm CMOS process, the prototype voltage reference occupies 0.058 mm2, including the AZ buffer and an on-chip timing generator. It outputs a reference voltage of 204.1 mV with a minimum supply voltage of 0.7 V. It achieves a TC of 18 ppm/° C from -40 ° C to 85 ° C and a PSRR of -75 dB at 100 Hz with only 200 μV ripple.