IN [1], there is a mistake in the timing diagram shown in Fig. 6. Switches S 1-S 4 are skipping some of the samples and the rate at which they are operating implies a TDM rate of 10 MHz, whereas (as described in [1]) this should be 20 MHz. In the updated Fig. 6, S 1-S 4 have been updated and a minor change has been made to the timing shown for switches Q₁ and Q₂, such that the correct TDM rate is indicated and no sample provided to the S/H stage via N1-N4 is skipped in the diagram. (Figure presented).

This article presents a novel in-package relative humidity (RH) sensor designed to enhance moisture detection within the chip encapsulation material, specifically epoxy molding compound (EMC). Traditional methods for assessing EMC moisture content, such as mass measurements, are time-consuming and incompatible with industrial reliability tests, limiting their use for real-time, in situ monitoring. To address these challenges, we propose an integrated capacitive sensor that directly measures moisture content within the encapsulation material. The sensor utilizes a heterogeneous electrode design to overcome the sensitivity limitations of conventional interdigital electrodes (IDEs). This design features sections of different widths, allowing selective wet chemical etching of the silicon dioxide layer using buffered hydrofluoric acid (BHF). By controlling the etching time, the silicon dioxide layer beneath the narrower sections is completely etched, while oxide pillars form under the wider sections, resulting in semifloating electrodes. The EMC fills the etched regions and wraps around the narrower sections, concentrating more electric field lines in the EMC and enhancing sensor sensitivity. Our proposed sensor achieves a capacitance change of 1 pF per 80% RH, improving sensitivity from 6.9 to 12.3 fF/%RH, with a 20% increase in relative capacitance change. A shielding layer is added to minimize parasitic capacitance effects, ensuring accurate measurements. The proposed sensor is fully CMOS-compatible and can monitor moisture-induced reliability risks, as well as assess packaging material aging. This work provides a cost-effective and reliable solution for in-package humidity monitoring in semiconductor applications.

This article presents an application-specific integrated circuit (ASIC) for battery-powered ultrasound (US) devices. The ASIC implements a novel energy-efficient high-voltage (HV) pulser that generates HV transmit (TX) pulses directly from a low-voltage (LV) battery supply. By means of a single off-chip inductor, energy is supplied to a US transducer in a resonant fashion, directly generating half-period sinusoidal HV pulses on the transducer, while consuming substantially less energy than a conventional class-D pulser. By recycling residual reactive energy from the transducer back to the input, the energy consumption is further reduced by more than 50%. The autocalibration techniques are leveraged to deal with tolerances of the inductor, transducer, and battery supply and thus maximize the energy efficiency. A prototype chip was fabricated in TSMC 0.18-μm HV BCD technology and used to drive external 120-pF capacitive micromachined US transducers (CMUTs) with a center frequency of approximately 2.5 MHz. Electrical measurements show that the prototype can generate pulses with a peak amplitude between 10 and 30 V accurate to within ±1 V. Acoustic measurements demonstrate successful ultrasonic pulse transmission and pulse-echo measurements. The prototype reaches a peak efficiency of 0.23 fCV ² , which is the highest reported to date for HV pulsers targeting US imaging.

This article presents a pitch-matched transceiver application-specific integrated circuit (ASIC) for a wearable ultrasound device intended for transfontanelle ultrasonography, which includes element-level 20-V unipolar pulsers with transmit (TX) beamforming, and receive (RX) circuitry that combines eightfold multiplexing, four-channel micro-beamforming (?BF), and subgroup-level digitization to achieve an initial 32-fold channel-count reduction. The ?BF is based on passive boxcar integration, merged with a 10-bit 40 MS/s SAR ADC in the charge domain, thus obviating the need for explicit anti-alias filtering (AAF) and power-hungry ADC drivers. A compact and low-power reference generator employs an area-efficient MOS capacitor as a reservoir to quickly set a reference for the ADC in the charge domain. A low-power multi-level data link, based on 16-level pulse-amplitude modulation, concatenates the outputs of four ADCs, providing an overall 128-fold channel-count reduction. A prototype transceiver ASIC was fabricated in a 180-nm BCD technology, and interfaces with a 2-D PZT transducer array of 16 × 16 elements with a pitch of 125 ?m and a center frequency of 9 MHz. The ASIC consumes 1.83 mW/element. The data link achieves an aggregate 3.84 Gb/s data rate with 3.3 pJ/bit energy efficiency. The ASIC's functionality has been demonstrated through electrical, acoustic, and imaging experiments.

This article presents an application-specific integrated circuit (ASIC) for catheter-based 3-D ultrasound imaging probes. The pitch-matched design implements a comprehensive architecture with high-voltage (HV) transmitters, analog front ends, hybrid beamforming analog-To-digital converters (ADCs), and data transmission to the imaging system. To reduce the number of cables in the catheter while maintaining a small footprint per element, transmission (TX) beamforming is realized on the chip with a combination of a shift register (SR) and a row/column (R/C) approach. To explore an additional cable-count reduction in the receiver part of the design, a channel with a combination of time-division multiplexing (TDM), subarray beamforming, and multi-level pulse amplitude modulation (PAM) data transmission is also included. This achieves an 18-fold cable-count reduction and minimizes the power consumption in the catheter by a load modulation (LM) cable driver. It is further explored how common-mode interference can limit beamforming gain and a strategy to reduce its impact with local regulators is discussed. The chip was fabricated in TSMC 0.18-m HV BCD technology and a 2-D PZT transducer matrix of 16 × 18 elements with a pitch of 160 m and a center frequency of 6 MHz was manufactured on the chip. The system can generate all required TX patterns at up to 30 V, provides quick settling after the TX phase, and has an reception (RX) power consumption of only 1.12 mW/element. The functionality and operation of up to 1000 volumes/s have been demonstrated in electrical and acoustic imaging experiments.

This paper presents a pitch-matched transceiver ASIC integrated with a 2-D transducer array for a wearable ultrasound device for transfontanelle ultrasonography. The ASIC combines 8-fold multiplexing, 4-channel micro-beamforming (μ BF) and sub-array-level digitization to achieve a 128-fold channel-count reduction. The μ BF is based on passive boxcar integration and interfaces with a 10-bit 40 MS/s SAR ADC in the charge domain, thus obviating the need for explicit anti-alias filtering and power-hungry ADC drivers. A compact and low-power reference generator employs an area-efficient MOS capacitor as a reservoir to quickly set a reference for the ADC in the charge domain. A low-power multi-level data link concatenates outputs of four ADCs, leading to an aggregate 3.84 Gb/s data rate. Per channel, the RX circuit consumes 2.06 mW and occupies 0.05 mm2.

This article presents a low-power and small-area transceiver application-specific integrated circuit (ASIC) for 3-D trans-fontanelle ultrasonography. A novel micro-beamforming receiver architecture that employs current-mode summation and boxcar integration is used to realize delay-and-sum on an N -element sub-array using N× fewer capacitive memory elements than conventional micro-beamforming implementations, thus reducing the hardware overhead associated with the memory elements. The boxcar integration also obviates the need for explicit anti-aliasing filtering in the analog front end, thus further reducing die area. These features facilitate the use of micro-beamforming in smaller pitch applications, as demonstrated by a prototype transceiver ASIC employing micro-beamforming on sub-arrays of N=4 elements, targeting a wearable ultrasound device that monitors brain perfusion in preterm infants via the fontanel. To meet its strict spatial resolution requirements, a 10-MHz 100- μ m-pitch piezoelectric transducer array is employed, leading to a per-element die area > 2 × smaller than prior designs employing micro-beamforming.

Intra-cardiac echography (ICE) probes (Fig. 32.2.1) are widely used in electrophysiology for their good procedure guidance and relatively safe application. ASICs are increasingly employed in these miniature probes to enhance signal quality and reduce the number of connections needed in mm-diameter catheters [1]-[5]. 3D visualization in real-time is additionally enabled by 2D transducer arrays with, for each transducer element, a high-voltage (HV) transmit (TX) part, to generate acoustic pulses of sufficient pressure, and a receive (RX) path, to process the resulting echoes. To achieve the required reduction in RX channels, micro-beamforming (BF), which merges the signals from a subarray using a delay-and-sum operation, has been shown to be an effective solution [3], [4]. However, due to the frame-rate reduction that is associated with BF, these designs cannot serve emerging high-frame-rate imaging modes (1000 volumes/s) like 3D blood-flow and elastography imaging. In-probe digitization has recently been investigated to provide further channel-count reduction, make data transmission more robust, and enable pre-processing in the probe [1]-[3]. However, these earlier designs have either no TX functionality [2], [3] or only low-voltage (LV) TX [1] integrated. Combining BF and digitization with area-hungry HV transmitters in a pitch-matched scalable fashion while supporting high-frame-rate imaging remains an unmet challenge. The work presented in this paper meets this target, enabled by a hybrid ADC, the small die size of which allows for co-integration with 65V element-level pulsers.

The integration of 2D ultrasonic transducer arrays and pitch-matched ASICs has enabled the realization of various 3D ultrasound imaging devices in recent years [1]-[3]. As applications such as 3D intravascular ultrasonography, intra-cardiac echocardiography, and trans-fontanelle ultrasonography call for miniaturization and improved spatial resolution, higher-frequency transducers (>5MHz) with a correspondingly smaller array pitch (<150m) are needed. Such devices generally employ a large number of transducer elements, calling for channel-count reduction in the ASIC while meeting stringent restrictions on per-element power consumption and die area. Micro-beamforming (BF) is an effective way of reducing channel count by performing a delay-and-sum operation on the echo signals received within a sub-array [1]. However, prior BF implementations employ per-element capacitive memory to realize the delay [1], [2], making it increasingly difficult to apply BF in smaller-pitch arrays.

In this article, an application-specific integrated circuit (ASIC) for 3-D, high-frame-rate ultrasound imaging probes is presented. The design is the first to combine element-level, high-voltage (HV) transmitters and analog front-ends, subarray beamforming, and in-probe digitization in a scalable fashion for catheter-based probes. The integration challenge is met by a hybrid analog-to-digital converter (ADC), combining an efficient charge-sharing successive approximation register (SAR) first stage and a compact single-slope (SS) second stage. Application in large ultrasound imaging arrays is facilitated by directly interfacing the ADC with a charge-domain subarray beamformer, locally calibrating interstage gain errors and generating the SAR reference using a power-efficient local reference generator. Additional hardware-sharing between neighboring channels ultimately leads to the lowest reported area and power consumption across miniature ultrasound probe ADCs. A pitch-matched design is further enabled by an efficient split between the core circuitry and a periphery block, the latter including a datalink performing clock data recovery (CDR) and time-division multiplexing (TDM), which leads to a 12-fold total channel count reduction. A prototype of $8{\times }9$ elements was fabricated in a TSMC 0.18- $\mu \text{m}$ HV BCD technology and a 2-D PZT transducer matrix with a pitch of $160 \mu \text{m}$ , and a center frequency of 6 MHz was manufactured on the chip. The imaging device operates at up to 1000 volumes/s, generates 65-V transmit pulses, and has a receive power consumption of only 1.23 mW/element. The functionality has been demonstrated electrically as well as in acoustic and imaging experiments.

In this letter, a compact high-voltage (HV) transmit circuit for dense 2-D transducer arrays used in 3-D ultrasonic imaging systems is presented. Stringent area requirements are addressed by a unipolar pulser with embedded transmit/receive switch. Combined with a capacitive HV level shifter, it forms the ultrasonic HV transmit circuit with the lowest reported HV transistor count and area without any static power consumption. The balanced latched-based level shifter implementation makes the design insensitive to transients on the HV supply caused by pulsing, facilitating application in probes with limited local supply decoupling, such as imaging catheters. Favorable scaling through resource sharing benefits massively arrayed architectures while preserving full individual functionality. A prototype of 8 × 9 elements was fabricated in the TSMC 0.18 μm HV BCD technology and a 160μm×160μm PZT transducer matrix is manufactured on the chip. The system is designed to drive 65-V peak-to-peak pulses on 2-pF transducer capacitance and hardware sharing of six elements allows for an area of only 0.008 mm2 per element. Electrical characterization as well as acoustic results obtained with the 6-MHz central frequency transducer are demonstrated.

This article presents a compact analog front-end (AFE) circuit for ultrasound receivers with linear-in-dB continuous gain control for time-gain compensation (TGC). The AFE consists of two variable-gain stages, both of which employ a novel complementary current-steering network (CCSN) as the interpolator to realize continuously variable gain. The first stage is a trans-impedance amplifier (TIA) with a hardware-sharing inverter-based input stage to save power and area. The TIA's output couples capacitively to the second stage, which is a class-AB current amplifier (CA). The AFE is integrated into an application-specific integrated circuit (ASIC) in a 180-nm high-voltage BCD technology and assembled with a 100 μm-pitch PZT transducer array of 8 × 8 elements. Both electrical and acoustic measurements show that the AFE achieves a linear-in-dB gain error below ±0.4 dB within a 36-dB gain range, which is > 2 × better than the prior art. Per channel, the AFE occupies 0.025 mm2 area, consumes 0.8 mW power, and achieves an input-referred noise density of 1.31 pA/√Hz.

This article presents an application-specific integrated circuit (ASIC) designed for intra-vascular ultrasound imaging that interfaces 64 piezoelectric transducer elements to an imaging system using a single micro-coaxial cable. Thus, it allows a single-element transducer to be replaced by a transducer array to enable 3-D imaging. The 1.5-mm-diameter ASIC is intended to be mounted at the tip of a catheter, directly integrated with a 2-D array of piezoelectric transducer elements. For each of these elements, the ASIC contains a high-voltage (HV) switch, allowing the elements to transmit an acoustic wave in response to an HV pulse generated by the imaging system. A low-noise amplifier then amplifies the resulting echo signals and relays them as a signal current to the imaging system, while the same cable provides a 3-V supply. Element selection and other settings can be programmed by modulating configuration data on the supply, thus enabling full synthetic aperture imaging. An integrated element test mode measures the element capacitance to detect bad connections to the transducer elements. The ASIC has been fabricated in a 0.18- μm HV CMOS technology and consumes only 6 mW in receive. Electrical measurements show correct switching of 30-V transmit pulses and a receive amplification with a 71-dB dynamic range, including 12 dB of programmable gain over a 3-dB bandwidth of 21 MHz. The functionality of the ASIC has been successfully demonstrated in a 3-D imaging experiment.

This paper presents an ultrasound transceiver application-specific integrated circuit (ASIC) directly integrated with an array of 12 × 80 piezoelectric transducer elements to enable next-generation ultrasound probes for 3D carotid artery imaging. The ASIC, implemented in a 0.18 µm high-voltage Bipolar-CMOS-DMOS (HV BCD) process, adopted a programmable switch matrix that allowed selected transducer elements in each row to be connected to a transmit and receive channel of an imaging system. This made the probe operate like an electronically translatable linear array, allowing large-aperture matrix arrays to be interfaced with a manageable number of system channels. This paper presents a second-generation ASIC that employed an improved switch design to minimize clock feedthrough and charge-injection effects of high-voltage metal–oxide–semiconductor field-effect transistors (HV MOSFETs), which in the first-generation ASIC caused parasitic transmis-sions and associated imaging artifacts. The proposed switch controller, implemented with cascaded non-overlapping clock generators, generated control signals with improved timing to mitigate the effects of these non-idealities. Both simulation results and electrical measurements showed a 20 dB reduction of the switching artifacts. In addition, an acoustic pulse-echo measurement successfully demonstrated a 20 dB reduction of imaging artifacts.

This article presents a low-noise transimpedance amplifier (TIA) designed for miniature ultrasound probes. It provides continuously variable gain to compensate for the time-dependent attenuation of the received echo signal. This time-gain compensation (TGC) compresses the echo-signal dynamic range (DR) while avoiding imaging artifacts associated with discrete gain steps. Embedding the TGC function in the TIA reduces the output DR, saving power compared to prior solutions that apply TGC after the low-noise amplifier. The TIA employs a capacitive ladder feedback network and a current-steering circuit to obtain a linear-in-dB gain range of 37 dB. A variable-gain loop amplifier based on current-reuse stages maintains constant bandwidth in a power-efficient manner. The TIA has been integrated in a 64-channel ultrasound transceiver application-specific integrated circuit (ASIC) in a 180-nm BCDMOS process and occupies a die area of 0.12 mm2. It achieves a gain error below ±1 dB and a 1.7 pA/ √ Hz noise floor and consumes 5.2 mW from a ±0.9 V supply. B-mode images of a tissue-mimicking phantom are presented that show the benefits of the TGC scheme.