This article presents a novel in-package relative humidity (RH) sensor designed to enhance moisture detection within the chip encapsulation material, specifically epoxy molding compound (EMC). Traditional methods for assessing EMC moisture content, such as mass measurements, are time-consuming and incompatible with industrial reliability tests, limiting their use for real-time, in situ monitoring. To address these challenges, we propose an integrated capacitive sensor that directly measures moisture content within the encapsulation material. The sensor utilizes a heterogeneous electrode design to overcome the sensitivity limitations of conventional interdigital electrodes (IDEs). This design features sections of different widths, allowing selective wet chemical etching of the silicon dioxide layer using buffered hydrofluoric acid (BHF). By controlling the etching time, the silicon dioxide layer beneath the narrower sections is completely etched, while oxide pillars form under the wider sections, resulting in semifloating electrodes. The EMC fills the etched regions and wraps around the narrower sections, concentrating more electric field lines in the EMC and enhancing sensor sensitivity. Our proposed sensor achieves a capacitance change of 1 pF per 80% RH, improving sensitivity from 6.9 to 12.3 fF/%RH, with a 20% increase in relative capacitance change. A shielding layer is added to minimize parasitic capacitance effects, ensuring accurate measurements. The proposed sensor is fully CMOS-compatible and can monitor moisture-induced reliability risks, as well as assess packaging material aging. This work provides a cost-effective and reliable solution for in-package humidity monitoring in semiconductor applications.

This study presents a novel approach for localized silver (Ag) nanoparticles (NPs) sintering using microheater arrays embedded within the Si substrate. By applying controlled pulse currents, these microheaters generate targeted heat pulses, enabling rapid and localized sintering while maintaining the surrounding device components at room temperature. This localized heating minimizes thermal stress caused by thermal expansion mismatches, as sintering completes within milliseconds. Compared to conventional sintering techniques, this method improves process efficiency, reduces power consumption, and provides precise spatial control over the sintered regions. The proposed approach offers a promising alternative for microelectronics packaging and integration, particularly in applications requiring precise thermal management.

This paper investigates the effects of three ageing factors (chemical, humidity, and temperature) and their interactions on the physical properties and degradation of silicone sealant used in microelectronic applications. The thermal degradation of silicone sealants was investigated by exposing samples to temperatures in the range of 150 up to 175 °C. Also, a set of samples were aged at 40 °C in a salt spray set-up with 100 % humidity in a salty atmosphere. Results showed detectable changes in the FTIR spectra of aged specimen as compared with the as-received sample. In all accelerated testing conditions, peak intensities decreased with ageing time, inferring that that the surface characteristics of the sealant is affected by ageing. Shear test results showed that with increasing the ageing time, the maximum shear stress in most cases has decreased in all ageing conditions. Also, it appears that samples with longer ageing times have experienced more elongation before failure. Results also show that salt spraying of specimens is associated with a decrease in the mechanical properties of the sealant, indicating the deleterious implications of ionic contaminations for the mechanical properties of samples.

Power MOSFET dies in the automotive industry are becoming larger (>5 × 5 mm) and thinner (<50 µm) to meet high-performance and lifetime requirements. Ensuring the mechanical robustness of these large ultrathin chips is crucial for reliable electronic devices and high-throughput packaging processes. The high aspect ratio and advanced chip designs incorporating trench technology present significant challenges in semiconductor assembly, packaging, and testing. This paper introduces an experimental front-end strategy aimed at strengthening the front side (FS) of large ultrathin dies using various die-top systems. Industry-equivalent 50 µm thick dummy power MOSFET dies were fabricated to evaluate the efficacy of different chip designs and materials, such as polyimide (PI), in mitigating fracture risks. Fabrication-induced stresses and warpage in the device layers were measured using a thin-film stress measurement tool. Additionally, the FS strength of the ultrathin dies was assessed using the three-point bending method, with the resulting data analyzed via two-parameter Weibull distribution plots. Results demonstrated that the deposition of 5 µm PI on the nitride die topside significantly increased die strength from 339 MPa to 760 MPa, with 5 µm PI proving more effective for die strengthening than 10 µm. The interaction between the metal-trench layer and the die was found to be critical to the robustness of ultrathin dies, influenced by the pattern and layout of the trenches. Die-top metallization designs, such as meandering patterns, showed promising improvements in die strength compared to standard designs. A proposed chip layout aims to maximize PI coverage for clip-bonded products on the die topside, leveraging its strengthening effect. The study also demonstrated that dummy reference chips can facilitate rapid and straightforward evaluation of extensive design experiments to identify robust chip designs.

This report demonstrates an innovative method to achieve large scale 20 μm pitch Cu-Cu direct bonding, utilizing lithographic stencil printing to transfer small-sized nano-copper (CuNPs) paste and employs a thermocompression method for CuNPs sintering to establish interconnections between copper-pillars and CuNPs bumps. Shear tests were conducted to characterize the bonding strength. High-throughput 20 μm pitch copper-to-copper direct bonding enables lower annealing temperatures for bulk-Cu to bulk-Cu bonding. Lithographic stencil printing is used to transfer the CuNPs paste, followed by sintering of the nanoparticles to establish interconnections. Shear tests and cross-section SEM were conducted to characterize the bonding strength and quality.

Copper nanoparticles (CuNPs) sintering for flip-chip interconnects is a promising solution for 3D and heterogeneous integration to overcome the limitation of solder materials. To this end, we perform the photolithographic stencil printing method to pattern CuNPs, and the form of flip-chip interconnects is completed after CuNPs sintering process. This paper aims to study the effect of sintering processing parameters (time, pressure, temperature) on the mechanical properties of CuNPs bumps when applying the novel method to approach the Cu interconnects. We fabricated seven groups of specimens of sintered CuNPs bumps, built with a diameter of 100 μm and sintered. The nanoindentation tests assessed the mechanical property to get Young's modulus and hardness. Results clarify that Young's modulus is strongly affected by pressure. An suggested combination of parameters (the 25 MPa and 260 °C for 15 min) give the highest modulus of 126 GPa and the hardness of 1.76 GPa. Moreover, the observations by scanning electron microscopy (SEM) reveal the microstructure and porosity evolution versus different processing parameters.

The next generation of satellites will need to tackle tomorrow's challenges for communication, navigation and observation. In order to do so, it is expected that the amount of satellites in orbit will keep increasing, form smart constellations and miniaturize individual satellites to make access to space cost effective. To enable this next generation of activities in space, it is vital to ensure the ability of these satellites to properly navigate themselves. This control starts with attitude measurement by the dedicated sensors on the satellite, commonly performed by sun position sensors. The state-of-the art is confronted by large signal distortions caused by light reflected by the Earth's albedo as well as keeping up with the satellite miniaturization trend. This work aims to address both these issues, by presenting a microfabricated albedo insensitive sun position sensor in silicon carbide with wafer-level integrated optics. The presented 10 mm×10 mm×1 mm system reaches a mean angular accuracy of 5.7° in a ±37° field-of-view and integrates an on-chip temperature sensor with a -3.9 mV K⁻¹ sensitivity in the 20 °C to 200 °C range.

This study presents the design and fabrication of an in-package relative humidity sensor for epoxy molding compound (EMC) packages. The sensor comprises shielded interdigital electrodes (SIDE) for in-situ monitoring of humidity absorption/desorption in the package encapsulation layer. A novel approach is employed in the device fabrication to maximize the electrical field lines to pass through the EMC and enhance the sensitivity. The manufactured wafer includes 6×6mm2 dies, each containing six identical capacitive sensors with an area of 480 × 620 μ m2. SU-8 through polymer vias (TPVs) with high aspect ratio were created to locally mold the sensors by EMC. The linear capacitance change with the relative humidity level is simulated in COMSOL Multiphysics. Three designs were compared, and the calibration results show the capacitance value of 1.54 pF and 5.85 pF before and after molding, respectively. The capacitance value stays within the range of 5.85 to 5.86 pF with less than 7 aF variation under different biasing voltages, indicating the stability and robustness of the capacitance.

The trend to 3D and heterogeneous integration enable driving multi-functional blocks in one package. Flip-chip integration is currently playing an important role and is based on solder joints. To overcome the limitations of solder joints, all-copper interconnects have been investigated to meet electrical, thermal, and reliability demands in 3D integration. The underfill process is widely applied in flip-chip encapsulation technology. We propose a novel wafer-scale all-Cu interconnect method combining epoxy-based photo-patternable polymer as self-aligned underfill layer with the patterned copper nanoparticles interconnects. The resulting test wafers were able to pattern 20 µm pitch copper nanoparticle-paste interconnects on both substrates with and without photoimageable polymer. The Cu paste was applied to form the interconnects and was sintered after bonding process. Free-standing nanocopper is sintered to obtain mechanical properties with a Young's modulus of 112 GPa. All-Cu interconnects with diameter of 50 µm and 100 µm were measured to achieve the specific contact resistance, ranging from 1.4 × 10-5O· cm2 to 1.0 × 10-5O· cm2 at different sintering temperature when epoxy-based underfill existing. And its resistivity was 4.54× 10-4 O· cm, compared to 5.86× 10-4O· cn for the all-Cu interconnects without underfill.

Wide bandgap (WBG) semiconductor technologies enable significant progress in the emergence of power modules. Power cycling at elevated temperatures causes crack or delamination failure, especially at the die-attached bonded interface in the long term. Therefore, the in-situ reliability investigation of power modules, materials, and semiconductor packages is of great significance for modern industries. The silicon carbide's higher bandgap energy, intrinsic thermal conductivity, and mechanical strength make it a great candidate for the next generation of semiconductor, designed to operate in harsh conditions. In this study, a thin-film reconfigurable silicon carbide (SiC) thermal test chip (TTC) is designed and fabricated for reliability assessment in harsh environments. The proposed TTC realizes in-situ power/thermal cycling tests at elevated temperatures as well as characterization of novel materials such as nanoparticle-based sintering materials in die-attach technology and high-temperature-compatible epoxy molding compounds. The chip is equipped with thin-film platinum microheaters to realize modular power mappings, and platinum resistive temperature detectors (RTD) to examine the thermal reliability by monitoring the precise changes of the internal junction-to-case thermal resistance.

Advances in semiconductor device manufacturing technologies are enabled by the development and application of novel materials. Especially one class of materials, nanoporous films, became building blocks for a broad range of applications, such as gas sensors and interconnects. Therefore, a versatile fabrication technology is needed to integrate these films and meet the trend towards device miniaturization and high integration density. In this study, we developed a novel method to pattern nanoporous thin films with high flexibility in material selection. Herein, Au and ZnO nanoparticles were synthesized by spark ablation and printed on a Ti/TiO2 adhesion layer, which was exposed by a lithographic stencil mask. Subsequently, the photoresist was stripped by a cost-efficient lift-off process. Nanoporous patterned features were thus obtained and the finest feature has a gap width of 0.6 μ fm and a line width of 2 μ fm. Using SEM and profilometers to investigate the structure of the films, it was demonstrated that the lift-off process had a minor impact on the microstructure and thickness. The samples presented a rough surface and high porosity, indicating a large surface-to-volume ratio. This is supported by the measured conductivity of Au nanoporous film, which is 12% of the value for bulk Au. As lithographic stencil printing is compatible with conventional lithographic pattering, this method enables further application on mass production of various nanoporous film-based devices in the future.