This article presents a novel in-package relative humidity (RH) sensor designed to enhance moisture detection within the chip encapsulation material, specifically epoxy molding compound (EMC). Traditional methods for assessing EMC moisture content, such as mass measurements, are time-consuming and incompatible with industrial reliability tests, limiting their use for real-time, in situ monitoring. To address these challenges, we propose an integrated capacitive sensor that directly measures moisture content within the encapsulation material. The sensor utilizes a heterogeneous electrode design to overcome the sensitivity limitations of conventional interdigital electrodes (IDEs). This design features sections of different widths, allowing selective wet chemical etching of the silicon dioxide layer using buffered hydrofluoric acid (BHF). By controlling the etching time, the silicon dioxide layer beneath the narrower sections is completely etched, while oxide pillars form under the wider sections, resulting in semifloating electrodes. The EMC fills the etched regions and wraps around the narrower sections, concentrating more electric field lines in the EMC and enhancing sensor sensitivity. Our proposed sensor achieves a capacitance change of 1 pF per 80% RH, improving sensitivity from 6.9 to 12.3 fF/%RH, with a 20% increase in relative capacitance change. A shielding layer is added to minimize parasitic capacitance effects, ensuring accurate measurements. The proposed sensor is fully CMOS-compatible and can monitor moisture-induced reliability risks, as well as assess packaging material aging. This work provides a cost-effective and reliable solution for in-package humidity monitoring in semiconductor applications.

This study presents the design and fabrication of an in-package relative humidity sensor for epoxy molding compound (EMC) packages. The sensor comprises shielded interdigital electrodes (SIDE) for in-situ monitoring of humidity absorption/desorption in the package encapsulation layer. A novel approach is employed in the device fabrication to maximize the electrical field lines to pass through the EMC and enhance the sensitivity. The manufactured wafer includes 6×6mm2 dies, each containing six identical capacitive sensors with an area of 480 × 620 μ m2. SU-8 through polymer vias (TPVs) with high aspect ratio were created to locally mold the sensors by EMC. The linear capacitance change with the relative humidity level is simulated in COMSOL Multiphysics. Three designs were compared, and the calibration results show the capacitance value of 1.54 pF and 5.85 pF before and after molding, respectively. The capacitance value stays within the range of 5.85 to 5.86 pF with less than 7 aF variation under different biasing voltages, indicating the stability and robustness of the capacitance.

Wide bandgap (WBG) semiconductor technologies enable significant progress in the emergence of power modules. Power cycling at elevated temperatures causes crack or delamination failure, especially at the die-attached bonded interface in the long term. Therefore, the in-situ reliability investigation of power modules, materials, and semiconductor packages is of great significance for modern industries. The silicon carbide's higher bandgap energy, intrinsic thermal conductivity, and mechanical strength make it a great candidate for the next generation of semiconductor, designed to operate in harsh conditions. In this study, a thin-film reconfigurable silicon carbide (SiC) thermal test chip (TTC) is designed and fabricated for reliability assessment in harsh environments. The proposed TTC realizes in-situ power/thermal cycling tests at elevated temperatures as well as characterization of novel materials such as nanoparticle-based sintering materials in die-attach technology and high-temperature-compatible epoxy molding compounds. The chip is equipped with thin-film platinum microheaters to realize modular power mappings, and platinum resistive temperature detectors (RTD) to examine the thermal reliability by monitoring the precise changes of the internal junction-to-case thermal resistance.