In this study, we introduced a hybrid Potts-phase field model to simulate the co-evolution of grain growth and pores migration in sintered silver layers. The Potts model is good at capture the grain growth dynamics, while the phase field model describes the evolution of the porous network. These models are coupled via a hybrid free energy function to achieve a realistic representation of the microstructure evolution. This study further extends the hybrid model by incorporating (a) a flexible exchange interaction matrix to model the crystal anisotropy in grain growth, (b) Glauber or Kawasaki dynamics to describe different diffusion mechanisms, and (c) the effect of pinning sites, representing impurity-driven grain boundary stabilization. The computational framework is implemented using Taichi Lang, which allows for efficient parallel simulations. Results show that the model effectively captures the long-term evolution of the sintered silver microstructure in good agreement with experimental observations. This hybrid model is a powerful tool to predict microstructural reliability of sintered silver die attach layers, supporting material design and process optimization for high-power electronic applications.

The heat produced within the device in its package depends on the power supplied to each IP block. The improper placement of an IP block with high power consumption can become a reliability risk for IC packages, as it can significantly affect the reliability of solder balls due to thermal, mechanical, and electrical factors. It also mitigates the effect of thermal cycling, because it depends upon heat management within the package. Improper IP block placement can block heat flow paths, which results in poor thermal dissipation and higher temperature which can create a higher strain on the solder balls affecting their lifetime. Therefore, it is crucial to understand the interplay between the correct placement of IP blocks and solder balls to enhance solder ball reliability. COMSOL-based simulation study will be done on a WLCSP (Wafer Level Chip Scale Package) mounted on a PCB board on which solder balls are connected to copper layers on the die and PCB sides. Variations in the placement of the IP blocks. Thermal cycling and the variations in the placement of the IP block within the package will be taken as a loading condition. Therefore, this influences the susceptibility of device failure due to solder ball fatigue. Based on board-level passive cycling, the solder balls which are located under the IP blocks are the most likely ones affected by this stress. The results will be analyzed to optimize the layout of the IP blocks, concerning accumulated plastic strain on the solder balls at different locations of the IP block placement. It can help to understand the influence of the position of the IP block, reduce stress concentration, and minimize thermal cycling effects, which leads to an increase in the reliability of the solders joint and IC package itself.

This paper investigates the effects of three ageing factors (chemical, humidity, and temperature) and their interactions on the physical properties and degradation of silicone sealant used in microelectronic applications. The thermal degradation of silicone sealants was investigated by exposing samples to temperatures in the range of 150 up to 175 °C. Also, a set of samples were aged at 40 °C in a salt spray set-up with 100 % humidity in a salty atmosphere. Results showed detectable changes in the FTIR spectra of aged specimen as compared with the as-received sample. In all accelerated testing conditions, peak intensities decreased with ageing time, inferring that that the surface characteristics of the sealant is affected by ageing. Shear test results showed that with increasing the ageing time, the maximum shear stress in most cases has decreased in all ageing conditions. Also, it appears that samples with longer ageing times have experienced more elongation before failure. Results also show that salt spraying of specimens is associated with a decrease in the mechanical properties of the sealant, indicating the deleterious implications of ionic contaminations for the mechanical properties of samples.

Silicon-Carbide (SiC) MOSFETs are widely used in high-power and high-efficiency applications such as electric vehicles and power supplies. However, long-term reliability remains a critical concern, particularly under extreme operating conditions. This work aims to explain the health monitoring of SiC metal oxide-semiconductor field effect transistors (MOSFETs) through precise junction temperature (T_j) profiling based on performed measurements. The study focuses on the temperature-dependent behavior of the on-resistance (RDS(on)), a key parameter that varies with the aging, degradation, and temperature of the device. By systematically measuring R_DS(on) at different temperatures and at various stages of the operating life of the device, we can establish a predictive model to assess the health of SiC MOSFETs. The importance of pulse duration of the drain current is stressed to avoid the self-heating effect with some device physics insights. The proposed methodology enables better understanding of the SiC MOSFET performance for future real-time condition monitoring, facilitating early failure detection and lifetime estimation. This approach provides valuable information for improving reliability and optimizing maintenance strategies in power electronics systems. Experimental results validate the effectiveness of the proposed method and give direction for future research opportunities.

A meshless method is used to simulate the Fluid-Structure Interaction (FSI) in a micropump intended to treat nerve injury. Conventional meshbased methods can suffer from mesh deformation and quality issues, and find it difficult to track the fluid-structure interface. The Material Point Method (MPM) combines Lagrangian material points with an Eulerian computational grid, thereby avoiding any mesh related problems. To simulate the valve dynamics in the micropump, MPM was used to analyze the effect of the valve length on the behaviour of the pump. A longer valve length takes longer to open, as it sticks to the valve seat, meaning the pump needs to generate more pressure to open the valve. This contribution shows that MPM simulations can be used to optimize the valve design for implantable micropumps.

Digital Twins (DT) play a key role in Industry 4.0 applications, and the technology is in the process of being mature. Since its conceptualisation, it has been heavily contextualised and often misinterpreted as being merely a virtual model. Thus, it is crucial to define it clearly and have a deeper understanding of its architecture, workflow, and implementation scales. This paper reviews the notion of a Digital Twin represented in the literature and analyses different kinds of descriptions, including several definitions and architectural models. A new fit-for-all definition is proposed which describes the underlying technology without being context-specific and also overcomes the pitfalls of the existing generalised definitions. In addition, the existing three-dimensional and five-dimensional models of the DT architecture and their characteristic features are analysed. A new simplified two-branched model of DT is introduced, which retains a clear separation between the real and virtual spaces and outlines the latter based on the two key modelling approaches. This model is then extended for condition monitoring of electronic components and systems, and a hybrid approach to Prognostics and Health Management (PHM) is further elaborated on. The proposed framework, enabled by the two-branched Digital Twin model, combines the physics-of-degradation and data-driven approaches and empowers the next generation of reliability assessment methods. Finally, the benefits, challenges, and outlook of the proposed approach are also discussed.

Semiconductor devices are commonly encapsulated with Epoxy-based Moulding Compounds (EMC) to form an electronic package. EMC typically occupies a large volume within a package, and thus, governs its thermomechanical behaviour. When exposed to high temperatures (150°C and above), electronic packages predominantly show oxidation of the outer layer of EMC. Oxidized EMC exhibits notably different material properties, resulting in a modified deformation pattern of a thermally aged package under varying thermal loads. As the oxidation layer grows in thickness, its mechanical properties also evolve, indicating distinct phases of the oxidized material at different stages of thermal ageing. Reflecting these changes (i.e., the current state of degradation) into a Finite Element (FE) model-based analysis can provide better insights into failure prediction and component reliability. It requires updating the geometry and material behaviour as a function of ageing. This paper presents a systematic procedure to build a continuously updated physics-based Digital Twin of a thermally aged flip-chip package that can represent intermediate oxidation stages. First, experimental measurements are carried out to quantify the growth of the oxidation thickness at 150°C and a diffusion-dominant mathematical model is proposed. Then, an accurate geometry of the test package is prepared with a parametric outer layer from all exposed sides of EMC to represent the oxidized layer at different stages of thermal ageing. Next, the experimental characterization of a few partially oxidized EMC specimens is done, and analytical methods are utilized to extract the thermomechanical properties of the oxidized EMC at different stages of ageing. Experimental warpage data of aged test packages are utilized to verify the defined material-model parameters that represent curing shrinkage, thermal expansion, glass transition, and corresponding elasticity moduli of the oxidized EMC at select stages of ageing. Then, a workflow to establish continuity in the material model is presented. Finally, the developed Digital Twin is utilized for an FE analysis to study the change in the trend of out-of-plane package deformations as a function of several stages of EMC oxidation.

Prognostic monitoring of power quad flat no-lead (PQFN) packages with four distinct silver pastes, each varying in material composition (pure-Ag and resin-reinforced hybridAg) and sintering processes (pressure-assisted and pressureless), was investigated in this study. The PQFN packages with silver sintered die-attach materials were subjected to thermal cycling tests (?55 ° C to 150 ° C), and the performance degradation was evaluated based on the following metrics: 1) electrical ON-state resistance RDSon monitored periodically at specific thermal cycling intervals and 2) transient thermal impedance Zth(t = 0.1 s) monitored online during thermal cycling. These measurements were further validated using acoustic microscopy imaging and cross-sectional inspection. The pressureless Ag-sintering material demonstrated comparable performance to pressure-assisted Agsintering, with a dense microstructure, and consistent electrical and stable thermal performance. Whereas the pressureless resinreinforced hybrid-Ag material exhibited degradation with a relative increase of 33% in RDSon, 38% in Zth(t = 0.1 s), and 67% delamination of the die-attach interface over 1000 cycles. These findings suggest that pressureless Ag-sintering may offer a viable alternative to pressure-assisted methods for lead (Pb)- free die-attachments, while resin-reinforced hybrid-Ag requires further development for improved thermomechanical reliability..

This paper introduces an ontology-based Digital Twin (DT) architecture for the lighting industry, integrating simulation models, data analytics, and visualization to represent luminaires. The ontology standardizes luminaire components, facilitating interoperability with design tools. The calculated ontology-level metrics suggest mid-level complexity with Size Of Vocabulary (SOV) at 37, Edge-to-Node Ratio (ENR) at 0.865, Tree Impurity (TIP) at 0, and Entropy Of Graph (EOG) at 2.61. A use case explores the utility of the ontology in the design phase across two different geographical locations, assessing environmental adaptability. The ontology captures opto-thermo-electric interactions, providing insights into luminaire performance. Results from inflating the DT and conducting simulations align with existing literature, indicating a degradation of around 12% over 8 years on the radiant flux. This ontology, up to the authors’ knowledge, is the first formal definition for the lighting industry, aiming to encompass the entire luminaire lifecycle. The current focus is on design and operational phases, with potential future enhancements to include real-time monitoring for performance evaluation and predictive maintenance. This work contributes to luminaire analysis and supports the development of sustainable lighting solutions in the industry.

The various application scenarios of triboelectric nanogenerator (TENG) have attracted increasing research interest, while one of the biggest challenges is the energy extraction efficiency. Due to the small and time-varying inherent capacitor in a TENG, the previous energy extraction techniques e.g., full-bridge rectifier (FBR) and bias-flip (BF) rectifier, performed not well. To extract more energy from TENG, this article proposed a fully integrated switched-capacitor (SC) rectifier with an electrostatic charge boosting (ECB) technique, achieving simultaneous extraction from the synchronized triboelectric energy and self-excited electrostatic energy. The proposed rectifier was fabricated in a 180-nm BCD process. With the proposed ECB technique, the theoretical analysis and measurements show a quadratically increasing output power with respect to the rectification voltage, attaining a constant maximum power point (MPP) at the breakdown voltage of the circuit. A maximum output power of 127.6 μ W is measured with a TENG fabricated in-house. Compared to a passive FBR, the proposed rectifier enhances the output power by 14 times.

Board level reliability can be of high interest for automotive electronic components when exposed to vibration-prone environments. However, the absence of an industry standard for board level vibration testing poses several challenges in establishing a well-characterized test setup. One of the challenges is that automotive applications can induce abnormal stresses on components that can lead to early failures in the field. Such loading conditions are not always covered in the current board level vibration test methods. This paper aims to correlate the stresses from automotive modules to board levels by measuring the printed circuit board (PCB) vibration spectrum. Firstly, the study compares and assesses several module board level vibration measurement units, such as LASER Doppler Vibrometer (LDV), strain gauges, and accelerometers. Experiments and simulations show that LDV enables good correlation with Micro-electro Mechanical Systems (MEMS) accelerometers. Secondly, the module-board interaction unveils insights into several module design features that impact the PCB vibration response and solder joint interconnect reliability. These findings underscore the necessity for the user to correctly validate the reliability of packages beyond board level testing, i.e., at the module level. This reliability test approach enables the translation of reliability test results from the lab to the field life of components once built in the final application equipment.

Lifetime analyses are crucial for ensuring the durability of new Light-emitting Diodes (LEDs) and uncertainty quantification (UQ) is necessary to quantify a lack of usable failure and degradation data. This work presents a new framework for predicting the lifetime of LEDs in terms of lumen maintenance, effectively quantifying the natural variability of lifetimes (aleatory) as well as the reducible uncertainty resulting from data scarcity (epistemic). Non-parametric survival models are employed for UQ of low-magnitude failures, while a new parametric interval prediction model (IPM) is introduced to characterize the uncertainty in high-magnitude lumen depreciation events and long-term extrapolated lifetimes. The width of interval-valued predictions reflects the inherent variability in degradation paths whilst the epistemic uncertainty, arising from data scarcity, is quantified by a statistical bound on the probability of the prediction errors for future degradation trajectories. A modified exponential flux decay model combined with the Arrhenius equation equips the IPM with physical information on the physics of LED luminous flux degradation. The framework is tested and validated on a novel database of LED degradation trajectories and in comparison to well-established probabilistic predictors. The results of this study support the validity of the proposed approach and the usefulness of the additional UQ capabilities.

Industrial assembly lines are the heartbeat of modern manufacturing, where precision and efficiency are paramount. This paper introduces a novel hybrid Explainable artificial intelligence (XAI) approach to enhance monitoring and analysis in industrial assembly. By fusing the power of vision anomaly detection models with the clarity of the gradient tree boosting algorithm, this framework not only boosts defect detection accuracy but also provides transparent, actionable insights. This synergy transforms how operators and engineers interact with AI, fostering trust and enhancing operational excellence.

Silver sintering offers a promising landscape for Pb-free die attachment in electronics packaging. However, the sintered interface properties are highly process-dependent and deviate from bulk silver properties. Conventional measurement methods do not adequately capture the die-attach application geometry. Hence, this study introduces a novel methodology for characterizing thin bond-line interfaces with high-conductive materials. The transient heat flux impedance ΔZth(t, Δx) was measured between two thermally sensitive devices interconnected using pressureless Ag-sintering material. A correction factor was derived, based on thermal half-space principles, to account for non-uniform heat spreading over the die-attach interface. Experimental findings estimate an effective conductivity of ∼115W/mk for the pressureless Ag-sintered interface. The measurement results were validated by measuring a SAC305 soldered interface, which exhibited ∼55 W/mK, and a non-conductive epoxy interface of ∼2.5 W/mK. Voids on the die-attach layer, resulting from material processing, were identified to influence the interface thermal behavior. An uncertainty analysis was further discussed, emphasizing equipment tolerances, measurement sensitivity, and geometrical and thermal anisotropies. The article concludes with a comparative summary of the proposed methodology against conventional methods, highlighting differences in working principle, thickness range, measurement parameters, and their advantages and limitations.

Low-temperature sintering technology of Ag nanoparticles is widely used in high-power electronic device packaging. Utilizing simulation methods to comprehend and control the microstructure and properties of Ag sintering materials has emerged as a prominent research area. This work uses the General Form PDE module in COMSOL to simplify the implementation of the phase field method. A two-particle model was established to explore the effects of different particle sizes and temperatures on the sintering neck of Ag nanoparticles. The two-particle model was expanded to multi-particle models and 3D models flexibly. This work presents the potential and limitations of these phase-field models, preparing for further multiphysics analysis and optimization of Ag sintering materials.

Solder fatigue is a key failure mode in the electronic industry. Monitoring the actual degradation of the solder under real-time conditions in any application would be extremely beneficial. In this chapter, we describe the combination of experimental material characterization with numerical finite element (FE) simulations to obtain a prognostics and health monitoring (PHM) methodology for LED drivers used in outdoor lighting applications. Experimental characterization of a new type of solder is described. A FE model is created of a typical component in electronic drivers. The calculated damage level and the collected life data correlate together and form a model for predicting the lifetime of the drivers at certain user condition. The developed PHM methodology helps in identifying and reporting the failure of the driver in real time or can be used for predicting the actual remaining useful life (RUL).

The demand for rapid advancement in AI, mobile and automotive markets is pushing the boundaries of electronic packaging, including heterogeneous integration, high-power packages, and large-die packaging. Against this backdrop, machine learning technologies emerge as dynamic tools for correlation building and classification, revolutionizing the traditional approaches to design, manufacturing, and testing in electronic packaging, as well as the Design for Reliability (DfR) methodologies.This paper reviews the most recent AI-assisted approach for electronic packaging and then focuses on the AI-assisted DfR (AI-DfR) approaches. Our examination reveals that AI methods have been adapted to meet the specific needs of electronic packaging. The industry’s anticipation for AI-DfR stems from its potential to address prevailing reliability design challenges, yet its multidisciplinary essence poses hurdles to swift progress. This review proposes future directions for AI-DfR’s development, spotlighting critical areas such as the quality and efficiency of finite element modeling, design and optimization of training models, selection of AI models, and maintenance and value enhancement strategies.

Power MOSFET dies in the automotive industry are becoming larger (>5 × 5 mm) and thinner (<50 µm) to meet high-performance and lifetime requirements. Ensuring the mechanical robustness of these large ultrathin chips is crucial for reliable electronic devices and high-throughput packaging processes. The high aspect ratio and advanced chip designs incorporating trench technology present significant challenges in semiconductor assembly, packaging, and testing. This paper introduces an experimental front-end strategy aimed at strengthening the front side (FS) of large ultrathin dies using various die-top systems. Industry-equivalent 50 µm thick dummy power MOSFET dies were fabricated to evaluate the efficacy of different chip designs and materials, such as polyimide (PI), in mitigating fracture risks. Fabrication-induced stresses and warpage in the device layers were measured using a thin-film stress measurement tool. Additionally, the FS strength of the ultrathin dies was assessed using the three-point bending method, with the resulting data analyzed via two-parameter Weibull distribution plots. Results demonstrated that the deposition of 5 µm PI on the nitride die topside significantly increased die strength from 339 MPa to 760 MPa, with 5 µm PI proving more effective for die strengthening than 10 µm. The interaction between the metal-trench layer and the die was found to be critical to the robustness of ultrathin dies, influenced by the pattern and layout of the trenches. Die-top metallization designs, such as meandering patterns, showed promising improvements in die strength compared to standard designs. A proposed chip layout aims to maximize PI coverage for clip-bonded products on the die topside, leveraging its strengthening effect. The study also demonstrated that dummy reference chips can facilitate rapid and straightforward evaluation of extensive design experiments to identify robust chip designs.

A significant challenge in the implementation of health monitoring systems for estimating the health state of devices is the lack of accurate information about design details. This challenge is particularly prominent in the field of power electronics, where both IC designers and converter designers are often hesitant to share information about their designs. Addressing this issue, this paper introduces a novel AI-driven digital twin modeling methodology that enables the detection and classification of failures in power semiconductors, particularly Wide Band Gap semiconductors. By employing AI-based system identification techniques, this method offers a noninvasive approach to health monitoring of power switches with high resolution, even while operating under real conditions. The proposed method has been validated by simulating wire bond failure in a SiC power MOSFET using MATLAB SIMULINK, and the results demonstrate its accuracy.

Electronic packages with solder interconnects, such as Chip Scale Packages (CSP) and Ball Grid Arrays (BGA), are extensively utilized in various applications, including cell phones, smartwatches, and electric vehicles. The advancements in technology and the features within these applications have led to an increase in power cycles within the packages. This combined with a reduced time to market makes their reliability testing more challenging. With the increased power cycles, even the small temperature variations (ΔT) within an Integrated Circuit (IC) package contribute to the increased susceptibility of devices to failures, often triggering a complex interplay of competing failure modes. Thus, it is crucial to understand the interplay between various failure mechanisms in real-world scenarios for evaluating and overseeing the dependability and efficiency of electronic systems. This paper presents an overview of the impact of small temperature variations on component reliability. In addition, a simulation-based preliminary study is carried out on a Wafer-Level Chip Scale Package (WLCSP) by implementing a thermal load corresponding to an active power cycle. The results are analyzed to locate possible failure locations within the solder bumps based on the accumulated plastic strains for different amplitudes of thermal load (ΔT). Finally, the necessity for a new testing strategy based on variable (ΔT) is highlighted.