Solder joint reliability related to failures due to thermomechanical loading is a critically important yet physically complex engineering problem. As a result, simulated behavior is oftentimes computationally expensive. In an increasingly data-driven world, it is popular to use efficient data-driven design schemes. Among the family of efficient optimization methods, Bayesian optimization with Gaussian process regression is a key representative. The authors argue that additional computational savings can be obtained from exploiting thorough surrogate modeling and selecting a design candidate based on multiple acquisition functions. This is feasible due to the relatively low computational cost, compared to the expensive simulation objective. This paper presents a novel heuristic framework for performing Bayesian optimization with adaptive hyperparameters across multiple optimization iterations. A comparative study shows the ability of adaptive Bayesian optimization to save on expensive objective evaluations with respect to the worst-performing regular Bayesian optimization scheme. As an engineering use case, the solder joint reliability problem is tackled by minimizing the accumulated non-linear creep strain under a cyclic thermal load. Results show that adaptive Bayesian optimization can at least match the performance of regular Bayesian optimization in terms of raw objective performance, but achieves this with half of the computational expense budget. This practical result underlines the methodological potential of the novel adaptive Bayesian data-driven methodology to achieve more efficient results and significantly cut optimization-related expenses. Lastly, to promote the reproducibility of the results, the data-driven implementations are made available on an open-source basis.

Due to the better performance of the Wide Band Gap (WBG) devices, there has been a paradigm shift toward WBG-based power modules for diverse applications like Electric Vehicles (EVs). However, the high parasitic inductance value of power modules hinders these devices from unlocking their full potential. Therefore, this paper comprehensively reviews SiC-based Single Side Cooling (SSC) power modules that benefit from low parasitic inductance. The paper also discusses the need to develop newer power modules using modern packaging methods. The surveyed power modules are categorized into three main groups, namely wire bonding, hybrid, and 3D packaging methods. This classification contains several vital parameters of the studied power modules, such as nominal and Double Pulse Tests (DPT) power ratings, parasitic inductance, size, etc. The main features and characteristics corresponding to the reviewed power modules' packaging methods and techniques are also briefly described. Finally, a thorough discussion about challenges and future trends is highlighted before concluding the paper.

The modeling of spectral characteristics of light-emitting diodes (LED) has been addressed in various studies. We extend the current state of knowledge by modeling the spectral characteristics of commercially available high-power LEDs, exhibiting a temperature-dependent degradation, by using a different modeling strategy. To this end, the state of the art approach of an additive superposition of probability density functions (PDF) is compared with an unsupervised machine learning approach called non-negative matrix factorization (NMF). The stress test data used in our modeling routine was collected for a period of 6000 hours at four different case temperatures between 55 C and 120 C. The results of the accelerated stress tests indicate a temperature-activated aging process, which can be described using the Arrhenius equation. By combining the Arrhenius equation with the modeling parameters, the spectral characteristics can be modeled for 6000 hours of stress at four different stress test temperatures. The introduced spectral modeling approach using non-negative matrix factorization achieves CIE 1976 UCS chromaticity differences primarily smaller than Δ u'v'≤ 0.001 and proves to be superior to superimposed probability density functions in terms of colorimetric reconstruction accuracy, modeling complexity and robustness against spectral outliers.

In this study, we introduced a hybrid Potts-phase field model to simulate the co-evolution of grain growth and pores migration in sintered silver layers. The Potts model is good at capture the grain growth dynamics, while the phase field model describes the evolution of the porous network. These models are coupled via a hybrid free energy function to achieve a realistic representation of the microstructure evolution. This study further extends the hybrid model by incorporating (a) a flexible exchange interaction matrix to model the crystal anisotropy in grain growth, (b) Glauber or Kawasaki dynamics to describe different diffusion mechanisms, and (c) the effect of pinning sites, representing impurity-driven grain boundary stabilization. The computational framework is implemented using Taichi Lang, which allows for efficient parallel simulations. Results show that the model effectively captures the long-term evolution of the sintered silver microstructure in good agreement with experimental observations. This hybrid model is a powerful tool to predict microstructural reliability of sintered silver die attach layers, supporting material design and process optimization for high-power electronic applications.

Silicon-Carbide (SiC) MOSFETs are widely used in high-power and high-efficiency applications such as electric vehicles and power supplies. However, long-term reliability remains a critical concern, particularly under extreme operating conditions. This work aims to explain the health monitoring of SiC metal oxide-semiconductor field effect transistors (MOSFETs) through precise junction temperature (T_j) profiling based on performed measurements. The study focuses on the temperature-dependent behavior of the on-resistance (RDS(on)), a key parameter that varies with the aging, degradation, and temperature of the device. By systematically measuring R_DS(on) at different temperatures and at various stages of the operating life of the device, we can establish a predictive model to assess the health of SiC MOSFETs. The importance of pulse duration of the drain current is stressed to avoid the self-heating effect with some device physics insights. The proposed methodology enables better understanding of the SiC MOSFET performance for future real-time condition monitoring, facilitating early failure detection and lifetime estimation. This approach provides valuable information for improving reliability and optimizing maintenance strategies in power electronics systems. Experimental results validate the effectiveness of the proposed method and give direction for future research opportunities.

This study investigates the microstructure evolution and mechanical behavior of bimodal-sized sintered copper (Cu) nanoparticles (NPs) under varying sintering pressures. Micro-pillar compression tests reveal a transition from collapse-dominated to compaction-driven deformation as sintering pressure increases. Transmission electron microscopy (TEM) and transmission Kikuchi diffraction (TKD) analyses identify a two-stage deformation mechanism—initial pore compaction followed by intragranular slip—fundamentally distinct from bulk Cu. Molecular dynamics (MD) simulations further reveal that large particles promote dislocation-mediated plasticity by accommodating intragranular slip, while small particles enhance load transfer through localized shear-compaction, together enabling uniform strain distribution and supporting the experimentally observed strain accommodation. The resulting microstructure achieves a combination of high yield strength (up to 320 MPa) and low elastic modulus (20 GPa), offering a compliant yet robust response. These findings elucidate a unique processing–structure–property relationship and provide a rational basis for designing porous metal interconnects capable of withstanding thermomechanical stresses in advanced electronic packaging.

This study investigates the interface strength and fracture behavior of sintered copper (Cu) nanoparticles (NPs) for all-Cu integration in advanced microelectronics packaging. Micro-cantilever bending tests on three configurations (Cu NP-notched, interface-notched and un-notched micro-cantilevers) were analyzed using scanning electron microscopy (SEM), transmission electron microscopy (TEM), transmission Kikuchi diffraction (TKD) and cohesive zone model (CZM). The interface-notched micro-cantilevers demonstrate superior fracture resistance, with a stress intensity factor (K_Q) of 2.88±0.10 MPa m^1/2, compared to 2.12±0.11 MPa m^1/2 for Cu NP-notched micro-cantilevers. Simulation results, consistent with experimental results, reveal that Cu NP-notched micro-cantilevers exhibit lower fracture resistance due to porosity and stress concentrations, while interface-notched micro-cantilevers show enhanced strength, attributed to robust bonding and reduced void distribution. Un-notched micro-cantilevers display superior load-bearing capacity, with cracks bypassing the interface and propagating through porous regions. Moreover, in un-notched micro-cantilevers, a synergistic deformation mechanism is observed, where crack propagation through the sintered Cu NPs coexists with plastic slip deformation in the Cu substrate. These findings highlight the strong interfacial bonding and effective stress transfer at the Cu substrate-sintered Cu NP interface, validating the feasibility of direct sintering using Cu NPs without additional coatings.

This paper investigates the effects of three ageing factors (chemical, humidity, and temperature) and their interactions on the physical properties and degradation of silicone sealant used in microelectronic applications. The thermal degradation of silicone sealants was investigated by exposing samples to temperatures in the range of 150 up to 175 °C. Also, a set of samples were aged at 40 °C in a salt spray set-up with 100 % humidity in a salty atmosphere. Results showed detectable changes in the FTIR spectra of aged specimen as compared with the as-received sample. In all accelerated testing conditions, peak intensities decreased with ageing time, inferring that that the surface characteristics of the sealant is affected by ageing. Shear test results showed that with increasing the ageing time, the maximum shear stress in most cases has decreased in all ageing conditions. Also, it appears that samples with longer ageing times have experienced more elongation before failure. Results also show that salt spraying of specimens is associated with a decrease in the mechanical properties of the sealant, indicating the deleterious implications of ionic contaminations for the mechanical properties of samples.

Electronic components are complex systems consisting of a combination of different materials, which undergo degenerative changes over time following the second law of thermodynamics. The loss of their quality or functionality is reflected in degraded performance or behaviour of electronic components, which can lead to failures during their operation lifetime. Thus, it is crucial to understand the physics of material degradation and the factors causing it to ensure component reliability. This paper focuses on the physics-of-degradation of packaging materials, which are typically exposed the most to the environmental and operating loads. The content of this article is organised into three parts. First, an overview of the packaging technology and encapsulating materials is presented. Then, the most common degradation-causing factors and package-associated failure modes are reviewed. Lastly, the hardware requirements are discussed, including specialised sensors, measurement techniques, and Digital Twins, to capture the degradation effects and facilitate component-level health monitoring for microelectronics.

The heat produced within the device in its package depends on the power supplied to each IP block. The improper placement of an IP block with high power consumption can become a reliability risk for IC packages, as it can significantly affect the reliability of solder balls due to thermal, mechanical, and electrical factors. It also mitigates the effect of thermal cycling, because it depends upon heat management within the package. Improper IP block placement can block heat flow paths, which results in poor thermal dissipation and higher temperature which can create a higher strain on the solder balls affecting their lifetime. Therefore, it is crucial to understand the interplay between the correct placement of IP blocks and solder balls to enhance solder ball reliability. COMSOL-based simulation study will be done on a WLCSP (Wafer Level Chip Scale Package) mounted on a PCB board on which solder balls are connected to copper layers on the die and PCB sides. Variations in the placement of the IP blocks. Thermal cycling and the variations in the placement of the IP block within the package will be taken as a loading condition. Therefore, this influences the susceptibility of device failure due to solder ball fatigue. Based on board-level passive cycling, the solder balls which are located under the IP blocks are the most likely ones affected by this stress. The results will be analyzed to optimize the layout of the IP blocks, concerning accumulated plastic strain on the solder balls at different locations of the IP block placement. It can help to understand the influence of the position of the IP block, reduce stress concentration, and minimize thermal cycling effects, which leads to an increase in the reliability of the solders joint and IC package itself.

Cold atmospheric plasma (CAP) is widely used in domains such as disinfection, surface treatment and food preservation. When generated in air, CAP is rich in reactive oxygen and nitrogen species (RONS), such as ozone (O3). A dielectric barrier discharge (DBD) is a reliable method to create CAP. We developed a double-sided (twin) surface DBD with novel ‘interfractal’ electrode geometries. This fractal configuration creates stronger electric fields than the customary interdigital line geometry. So, CAP is produced more effectively, resulting in higher RONS concentrations. The performance of interfractal electrodes was compared to that of interdigital electrodes (IDE) in atmospheric air. Nanopulsed powering was used, since it is the most efficient for powering DBDs. Electrical and chemical characteristics (such as ozone level) were assessed. The results show that interfractal electrodes enhance the electric field, conduction current and ozone yield.

This review is aimed at providing an overview of the technologies of currently-available UVC LEDs, on the challenges that these devices have to face, and on the peculiar features that these modern solid-state emitters exhibit. In particular, this paper is aimed at serving as a bridge between device developers and system manufacturers, by increasing awareness of the differences, both in terms of reliability and operation, that AlGaN-based UVC LEDs show with respect to their visible InGaN/GaN-based counterparts. In this view, this work reports performance and lifetime figures of both commercially-available and research-grade LEDs, showing their limitations in terms of temperature- and current-dependency of the emission spectrum. Both catastrophic and gradual processes that lead to device degradation are discussed, with a particular focus on the kinetics that device properties exhibit during prolonged operation. Moreover, also package-related degradation processes are investigated, which stand-out due to the peculiar structures and materials required to sustain both high-energy UV photons and high localized self-heating, while maximizing the optical efficiency of the LEDs. Ultimately, the data reported within this paper should help the final user in predicting and mitigating degradation effects, while also serving as a reference to manufacturers for the improvement of next generation devices.

Sintered Cu nanoparticles (NPs) are promising for high-performance electronics due to their excellent thermal and electrical conductivity, as well as mechanical reliability. This study investigates the microscale mechanical behavior of sintered Cu NPs with a bimodal particle size distribution, focusing on strain rate and temperature effects. Micro-pillar compression tests were performed across strain rates of 0.0001 s⁻¹ to 0.01 s⁻¹ and temperatures from 25 °C to 350 °C. Results show that higher strain rates enhance yield strength through strain-rate hardening, while elevated temperatures lead to thermal softening and reduced mechanical stability. The Anand viscoplastic model accurately predicts these deformation behaviors. Microstructural analysis via scanning electron microscopy (SEM) and transmission electron microscopy (TEM) reveals localized deformation at 175 °C, with dislocations concentrated near the top surface and persistent porosity below, whereas at 350 °C, re-sintering and grain boundary diffusion create a denser microstructure. Phase-field fracture modeling further elucidates crack propagation, emphasizing the role of pore size and temperature. This combined experimental and modeling approach enhances understanding of viscoplastic deformation and fracture mechanisms in sintered Cu NPs, informing their use in interconnects, power electronics and thermal management systems.

A meshless method is used to simulate the Fluid-Structure Interaction (FSI) in a micropump intended to treat nerve injury. Conventional meshbased methods can suffer from mesh deformation and quality issues, and find it difficult to track the fluid-structure interface. The Material Point Method (MPM) combines Lagrangian material points with an Eulerian computational grid, thereby avoiding any mesh related problems. To simulate the valve dynamics in the micropump, MPM was used to analyze the effect of the valve length on the behaviour of the pump. A longer valve length takes longer to open, as it sticks to the valve seat, meaning the pump needs to generate more pressure to open the valve. This contribution shows that MPM simulations can be used to optimize the valve design for implantable micropumps.

The reliability of solder joints plays an increasingly important role in power electronics. The thermal fatigue experienced due to the temperature fluctuations cause catastrophic failures. However, the ability to predict the fatigue for different thermal cycles is lacking. Experimental or simulation based approaches are typically too expensive to be conducted for a wide range of thermal loading conditions. A physics informed Long Short-Term Memory (PI-LSTM) is proposed here for predicting the plastic strain and related fatigue lifetime in solder joints. The LSTM model is trained on data generated by FEM simulations, enhanced by incorporating the flow rule into the loss function. The PI-LSTM accurately predicts the plastic strain and the stress components, enabling efficient reliability predictions. Using different reliability models, the estimated cycles to failure are found to be in close agreement with those from conventional FEM simulations, demonstrating the PI-LSTM's capability for reliability assessments.

Triboelectric nanogenerator (TENG), advantageous in high energy density and flexibility, is promising as a sustainable energy source but can hardly be used to power edge devices directly due to its high-voltage AC output and varying capacitive impedance. To address it, this work proposes a power-conditioning interface with a fully integrated dual synchronous switch harvesting on capacitors (D-SSHC) rectifier for triboelectric energy extraction. Furthermore, a full digital duty-cycle-based (DCB) maximum power point tracking (MPPT) algorithm is developed to optimize the energy harvesting efficiency with simple implementation and continuous tracking. Designed and fabricated in a 0.18-μm BCD process, the proposed interface can extract energy at a maximum output voltage of 70 V. According to the measurement results, it achieves 99% MPPT efficiency and an energy extraction improvement of 598% compared to a full-bridge rectifier.

We report on the degradation dynamics and mechanisms of commercially available green high-power light-emitting diodes (LEDs) with a peak wavelength of 522 nm. The stress tests were carried out for up to 8800 hours with forward currents ranging from 350 mA to 1000 mA at junction temperatures between 86 C and 155 C. Two complementary test designs were used to isolate temperature- and current-driven effects. The results of the accelerated tests reveal the following key findings: 1.) A square-root-time-dependent loss in the quantum wells caused by the generation of point defects, leading to up to 90 % flux reduction within the first 500 hours at low forward currents. 2.) A logarithmic decay governed by defect-induced carrier-injection loss, evident above I_EQE,max and accompanied by a spectral red shift. 3.) A temperature-activated blue shift with an activation energy of E_a =0.23 eV, indicating the coexistence of competing degradation mechanisms. The interplay between different mechanisms results in an enhanced device lifetime at higher stress temperatures and stands in contrast to previous findings reported in the literature. 4.) The isothermal stress test indicates a cubic acceleration of degradation with carrier density, implicating Auger-Meitner-generated hot electrons in defect formation. These insights provide guidance for mitigating reliability issues of green high-power LEDs in future devices.

Electronic packages with solder interconnects, such as Chip Scale Packages (CSP) and Ball Grid Arrays (BGA), are extensively utilized in various applications, including cell phones, smartwatches, and electric vehicles. The advancements in technology and the features within these applications have led to an increase in power cycles within the packages. This combined with a reduced time to market makes their reliability testing more challenging. With the increased power cycles, even the small temperature variations (ΔT) within an Integrated Circuit (IC) package contribute to the increased susceptibility of devices to failures, often triggering a complex interplay of competing failure modes. Thus, it is crucial to understand the interplay between various failure mechanisms in real-world scenarios for evaluating and overseeing the dependability and efficiency of electronic systems. This paper presents an overview of the impact of small temperature variations on component reliability. In addition, a simulation-based preliminary study is carried out on a Wafer-Level Chip Scale Package (WLCSP) by implementing a thermal load corresponding to an active power cycle. The results are analyzed to locate possible failure locations within the solder bumps based on the accumulated plastic strains for different amplitudes of thermal load (ΔT). Finally, the necessity for a new testing strategy based on variable (ΔT) is highlighted.

The ability to accurately predict the reliability and lifetime of electronics is of great importance to the industry. The failure of the solder joint is of particular interest for these predictions, because of their susceptibility to failure under thermo-mechanical stress. However, the experimental or even conventional simulation techniques employed to estimate the lifetime of a solder joint are often too expensive or time consuming to be of practical use. Therefore, this work introduces a physics-informed Long Short-Term Memory (LSTM) to predict the plastic strain in the critical area of the solder joint. The predicted values are in agreement with the values gained from finite elements, thereby demonstrating the advantage of applying the proposed methodology.

Board level reliability can be of high interest for automotive electronic components when exposed to vibration-prone environments. However, the absence of an industry standard for board level vibration testing poses several challenges in establishing a well-characterized test setup. One of the challenges is that automotive applications can induce abnormal stresses on components that can lead to early failures in the field. Such loading conditions are not always covered in the current board level vibration test methods. This paper aims to correlate the stresses from automotive modules to board levels by measuring the printed circuit board (PCB) vibration spectrum. Firstly, the study compares and assesses several module board level vibration measurement units, such as LASER Doppler Vibrometer (LDV), strain gauges, and accelerometers. Experiments and simulations show that LDV enables good correlation with Micro-electro Mechanical Systems (MEMS) accelerometers. Secondly, the module-board interaction unveils insights into several module design features that impact the PCB vibration response and solder joint interconnect reliability. These findings underscore the necessity for the user to correctly validate the reliability of packages beyond board level testing, i.e., at the module level. This reliability test approach enables the translation of reliability test results from the lab to the field life of components once built in the final application equipment.