The rapid growth of generative Artificial Intelligence (AI), automotive electrification and Internet of Things (IoT) is driving an unprecedented demand for high-performance Integrated Circuits (ICs), projected to push the semiconductor industry to a $1 trillion business by 2030 (Burkacky et al., 2022; PWC, 2025). This drove the adoption of advanced process (FinFET, Gate-All-Around, Forksheet, CFET, Backside Power Delivery Network) and 3D package technologies (chiplets, Heterogeneous Integration, Co-packaged Optics). Unfortunately, component stacking in 3D ICs such as Package-on-Package (PoP) products creates an optical barrier during Electrical Fault Isolation (EFI). This paper presents a novel Failure Analysis (FA) hardware and sample preparation solution that enables System-Level FA on mobile System-on-a-Chip (SoC) PoP devices, where the DRAM is stacked atop the logic controller device. The primary challenge in performing EFI on the bottom die is providing direct line-of-sight (LoS) access while preserving the top DRAM functionality through extremely small interconnects called Through Interposer Vias (TIVs). For the first time, this groundbreaking hardware solution overcomes the challenge of connecting a DRAM atop the SoC silicon, utilizing the smallest possible interposer pin pitch (∼210 um) and advanced DRAM card design that incorporates stringent design rules to enable up to 6.3 Gbps using a DDR training test and runs standard Android stress applications. The results of the FA hardware solution for SLT platform will be discussed, together with several FA use cases that were enabled through this innovative solution. Lastly, this paper will discuss the limitations of this hardware, together with opportunities for improvement and further work. This novel solution paves the way for the failure analysis of 3D IC devices on a system level platform, which are utilized not only in mobile applications, but also for cloud, server, and quantum computing ICs assembled in complex packages.

The evolution in modern-day electronics extends beyond miniaturization and significantly increases the number of power cycles operating with low temperature swings (few tens of degrees). This shift has raised the reliability requirements and expectations for electronics systems to last longer. The transition of vehicles and autonomous systems to zonal architectures, driven by electrification, has increased power-on hours of electronic components, leading to higher system complexity and more challenging reliability testing. Currently, standardized stress- based tests and predictive models have constraints, as they are designed for large temperature swings and are inaccurate for evaluating low T conditions. Additionally, the damage caused by Δ millions of low thermal swings is less explored in simulation and qualification, making it important to analyze the influence of low ΔT on solder joints to understand field reliability risks.An Arduino-based testing setup was developed to apply active thermal cycles to WLCSP40 using relay-controlled switching with 6-second cycles. Samples were tested from 50k to 800k cycles to analyze the long-term damage accumulation under such conditions. In addition to experiments, a thermomechanical simulation in COMSOL incorporated ΔT values obtained from thermal camera characterization to establish realistic boundary conditions. It helps to correlate experimental results and identify critical locations within the solder joints where damage is most likely to occur.Cumulative plastic strain analysis and cross-sectional imaging revealed cracks in the solder bulk at 40 °C, demonstrating microstructural fatigue under low ΔT cycling. Furthermore, based on strain per cycle values, the results exhibit how the active and passive thermal cycles differ.

Sintered Cu nanoparticles (Cu NPs) are promising interconnection materials for high-temperature power electronics, yet how their authentic three-dimensional pore architecture governs microscale deformation remains unclear. Here, synchrotron nano-computed tomography (nano-CT) was combined with in-situ micropillar compression, explicit dynamic elastoplastic finite element analysis, and TEM/TKD characterization to interrogate sintered Cu NPs. The nano-CT voxel size was 45 nm, and the reconstructed volume corresponded to a cylinder 16 µm in diameter and 10 µm in height. The average sectional porosity was 12.44%, with a systematic discrepancy between two-dimensional and three-dimensional porosity quantification. During loading, the porosity decreased to 9.55% while the pore aspect ratio increased from 1.82–2.35. Finite element analysis further showed pronounced pore-adjacent stress/strain localization at the elastic–plastic transition, with local stress and equivalent plastic strain reaching 650 MPa and 1.7 × 10⁻², compared with 250 MPa and 1.1 × 10⁻³ in adjacent regions. The GND density increased by 95.9% at a compressive strain of 26%, linking pore-induced strain gradients to dislocation accumulation. These results quantitatively connect authentic three-dimensional pore architecture, local deformation localization, and dislocation-mediated strengthening in sintered Cu NPs. Highlights Synchrotron nano-CT (45 nm voxel size) reconstructed a 16 × 10 µm cylindrical volume of sintered Cu NPs and resolved the authentic 3D pore network. Sectional porosity was 12.44%, and 2D/3D quantification showed a systematic discrepancy, with porosity decreasing to 9.55% and pore aspect ratio increasing from 1.82 to 2.35 during compression. Pore-adjacent localization was quantified at the elastic–plastic transition, with local stress/PEEQ reaching 650 MPa and 1.7 × 10⁻² versus 250 MPa and 1.1 × 10⁻³ in adjacent regions. A 95.9% increase in GND density at 26% compressive strain links pore-induced strain gradients to dislocation accumulation and strain-gradient-driven strengthening.

Due to the better performance of the Wide Band Gap (WBG) devices, there has been a paradigm shift toward WBG-based power modules for diverse applications like Electric Vehicles (EVs). However, the high parasitic inductance value of power modules hinders these devices from unlocking their full potential. Therefore, this paper comprehensively reviews SiC-based Single Side Cooling (SSC) power modules that benefit from low parasitic inductance. The paper also discusses the need to develop newer power modules using modern packaging methods. The surveyed power modules are categorized into three main groups, namely wire bonding, hybrid, and 3D packaging methods. This classification contains several vital parameters of the studied power modules, such as nominal and Double Pulse Tests (DPT) power ratings, parasitic inductance, size, etc. The main features and characteristics corresponding to the reviewed power modules' packaging methods and techniques are also briefly described. Finally, a thorough discussion about challenges and future trends is highlighted before concluding the paper.

This work proposes a nondestructive framework to track the time- and depth-resolved evolution of oxide traps in 4H-SiC metal-oxide-semiconductor (MOS) structures during time-dependent dielectric breakdown (TDDB) stress. The approach combines time-resolved gate admittance measurements with a distributed oxide admittance model and frequency-temperature depth mapping to reconstruct the measured dispersion at flatband voltage and recover nonuniform oxide trap profiles without imposing an a priori spatial distribution. Applied to long duration negative-bias TDDB, the extracted profiles reveal a strongly depth-nonuniform and field-accelerated defect build-up: higher stress not only increases the trap population, but also broadens the active defect region deeper into the oxide as breakdown is approached. By tracking the average trap density and the centroid of oxide trapped charge in the probed oxide region, we quantify the spatial evolution and relate it to the concurrent transients in gate leakage current, flatband voltage shift, and increment of interface trap density, without relying on destructive techniques, such as transmission electron microscopy, thus preserving the device for continuous evaluation. The same methodology is further demonstrated on stressed silicon carbide (SiC) power mosfets, supporting device-level relevance and providing a workflow for depth-resolved characterisation of SiC gate oxide degradation under negative stress.

Pressureless sintered Ag pastes are promising die-attach materials for power electronics, yet practical sintering-profile optimization still relies heavily on trial-and-error, and the link from thermal kinetics to fracture-relevant microstructure and strength remains insufficiently established. In this work, a thermal-kinetics-guided workflow was developed to design paste-specific pressureless sintering profiles for two commercial Ag pastes (a spherical-particle paste and a flake-based paste) and to interpret the resulting strength–fracture response using SEM-based, heterogeneity-aware learning. Multi-heating-rate TGA was used to define the conversion fraction (α), while DSC was used to identify the dominant thermal-event window and extract the characteristic peak temperature for Arrhenius pairing. The TGA-defined conversion evolution was then modeled using a JMAK/Avrami form with Arrhenius temperature dependence to predict the isothermal holding time required to reach a target conversion at a selected dwell temperature. Relative to supplier-recommended profiles, the optimized profiles increased die-shear strength by 35% for the spherical-particle paste and by 206% for the flake-based paste, and promoted a fracture-mode transition from interfacial debonding toward mixed/cohesive fracture. Pearson/Ridge baselines and attention-based multiple-instance learning (MIL) linked strength and fracture-mode distribution to porosity/connectivity-related descriptors; paste-wise normalization mitigated paste-specific baselines and enabled MIL to reveal profile-induced microstructure–performance co-variation. Overall, this study establishes a practical workflow that couples thermal-kinetics-guided profile design with mechanical and fractographic validation and interpretable microstructure–property attribution, supporting mechanism-informed optimization of pressureless sintered Ag die-attach pastes.

Organ-on-Chip (OoC) devices enable controlled replication of physiological microenvironments and are increasingly used in biomedical engineering and drug discovery. This study presents a comprehensive 3D simulation-based characterization of mass transport and mechanical properties of a silicon-based Barrier-on-Chip (BoC) device comprising two stacked microfluidic channels separated by a porous Si3N4 membrane. Steady-state laminar flow simulations are performed to obtain the velocity field, after which transient convection-diffusion simulations are conducted to evaluate species transport toward and across the membrane. The mechanical performance of the membrane is analyzed using coupled Fluid-Structure Interaction (FSI) simulations with effective material properties accounting for porosity. Three flow configurations namely coflow, counter-flow, and single-channel flow are investigated across four volumetric flow rates. The results show that both flow configuration and flow rate strongly influence concentration distributions along the membrane. Counter-flow produces the strongest axial concentration gradient, which becomes more spatially uniform at higher flow rates as convection-dominated transport increasingly governs the system. Higher flow rates also result in larger membrane deflections, with counter-flow producing deflections approximately two orders of magnitude greater than co-flow at low flow rates for both configurations. Wall shear stress increases linearly with flow rate, spanning the physiologically relevant ranges for intestinal epithelial and blood-brain barrier endothelial cells. These findings provide quantitative design guidelines for selecting flow configurations and rates based on target concentration gradients, shear stress levels, and mechanical constraints in BoC applications.

Accurate lifetime prediction of power semiconductor devices is critical for the reliability of power electronic systems. Power cycling tests generate only a small number of failure samples due to their high cost and long duration. This data scarcity makes it difficult to train reliable prediction models. At the same time, modern deep learning models require significant AI expertise to configure and tune, which creates a barrier for reliability engineers. To address these two problems, this paper proposes a domain-constrained multi-agent framework for automated remaining useful life (RUL) prediction of power semiconductor devices. The framework integrates three collaborative agents: a Stats Agent for statistical reliability assessment, a Physics Agent for physical plausibility validation, and a Model Agent for algorithm selection and hyperparameter tuning. A Central Controller manages the workflow and coordinates agent communication. The agents interact through a Propose-Critique-Refine (PCR) mechanism, in which the Model Agent proposes configurations and the other two agents critique them from statistical and physical perspectives. This iterative negotiation eliminates the need for manual parameter tuning. The framework is validated on the NASA IGBT accelerated aging dataset under Leave-One-Device-Out Cross-Validation. Results show that the framework achieves an R2 of 0.914 at a 50% observation ratio and remains above 0.79 even at 30%, demonstrating strong generalization under limited data conditions.

Modeling and monitoring advanced power semi-conductor packages are challenging due to their multiphysics behavior, structural complexity, and the high computational cost associated with detailed models. Conventional high-fidelity approaches, such as finite element models, provide high accuracy but are often unsuitable for applications like health monitoring, while purely data-driven models may lack physical interpretability and robustness under degradation.This paper proposes the concept of a multi-agent digital twin framework to address these challenges by decomposing the overall system into interconnected virtual domains with different roles and fidelity levels. The approach is demonstrated for health monitoring of a SiC MOSFET in a DC-DC buck converter. A three-agent architecture is implemented, consisting of a temporal ANN for system identification, a decision layer for failure detection and localization, and a parametric reduced-order thermal model for failure assessment. Experimental results show that the proposed framework can accurately identify system behavior, detect and localize failures, and quantify parameter variations associated with degradation.

The paper presents a degradation for remaining useful lifetime framework for smart power stages (SPS) with an integrated temperature sensor for electronic control units (ECU). A reduced order state space model with physically meaningful time constants is derived from finite element simulations. The state space model is the core of the damage estimation of the SPS during operation. A framework for remaining useful lifetime estimation is presented simulating degradation based on an estimated mission profile for cars. Temperature cycles are extracted and used to estimate the time constant drift representing package degradation. An exemplary approach on how to integrate degradation monitoring into a lifetime approximation of the package is presented. The state space model is extended for estimator based predictions to integrate the model in future test benches for real life monitoring and remaining useful life predictions of active devices.

With the rapid development of power electronics, power modules are required to achieve higher power density, wider operating temperature ranges, faster switching speed, and improved reliability. Large area sintering (LAS), due to its high electrical and thermal conductivity, has been widely recognized as a promising interconnection technology for power module packaging. Nevertheless, several challenges remain, including copper oxidation, package warpage, organic binder burnout and gas exhaust, and other processing-related issues. This article reviews recent research and patents on LAS technology, covering its background, classification, key challenges, and possible solutions. Based on the currently dominant process conditions and sintering materials, different LAS approaches are systematically summarized. Furthermore, three critical issues are highlighted, including organic burnout and excessive exhaust remaining, power module warpage, and copper oxidation control. For each challenge, the related reliability issues, current solutions, and future research directions are reviewed.

Serving as a significant attachment component, Active Metal Brazed (AMB) substrates are prone to oxidation during storage and processing. The copper surface oxidation of AMB substrates seriously affects the reliability of high-power modules. The formation of Cu2O/CuO oxide layer on the surface degrades interfacial qualities in subsequent packaging processes, including sintering, wire-bonding, and transfer-molding. To investigate the mechanism behind, this paper constructs a physically grounded multiscale oxidation framework that explicitly bridges molecular dynamics with reactive force field (ReaxFF-MD) and mesoscale continuum modeling. For ReaxFF-MD simulations, it aims to resolve oxygen adsorption, dissociation, diffusion behavior, and Cu-O network formation on the Cu(100), Cu(110), and Cu(111) surfaces at temperatures of 300 K and 600 K. Diffusion coefficients and interface reaction kinetic parameters are then quantitatively extracted from MD simulations and transferred as a bridge in reaction-diffusion continuum model with flux damping governed by a characteristic structural thickness. The results demonstrate that the early oxidation process of the copper surface is modulated by structural evolution and orientation anisotropy. The proposed multiscale framework provides a physical mechanism basis for understanding the early oxidation mechanism of copper and its impact on the reliability of AMB packaging.

Solder joint reliability related to failures due to thermomechanical loading is a critically important yet physically complex engineering problem. As a result, simulated behavior is oftentimes computationally expensive. In an increasingly data-driven world, it is popular to use efficient data-driven design schemes. Among the family of efficient optimization methods, Bayesian optimization with Gaussian process regression is a key representative. The authors argue that additional computational savings can be obtained from exploiting thorough surrogate modeling and selecting a design candidate based on multiple acquisition functions. This is feasible due to the relatively low computational cost, compared to the expensive simulation objective. This paper presents a novel heuristic framework for performing Bayesian optimization with adaptive hyperparameters across multiple optimization iterations. A comparative study shows the ability of adaptive Bayesian optimization to save on expensive objective evaluations with respect to the worst-performing regular Bayesian optimization scheme. As an engineering use case, the solder joint reliability problem is tackled by minimizing the accumulated non-linear creep strain under a cyclic thermal load. Results show that adaptive Bayesian optimization can at least match the performance of regular Bayesian optimization in terms of raw objective performance, but achieves this with half of the computational expense budget. This practical result underlines the methodological potential of the novel adaptive Bayesian data-driven methodology to achieve more efficient results and significantly cut optimization-related expenses. Lastly, to promote the reproducibility of the results, the data-driven implementations are made available on an open-source basis.