The increasing complexity of electronic systems in autonomous electric vehicles necessitates robust methods for forecasting the degradation of critical components such as printed circuit boards (PCBs). Various time series forecasting methods have been investigated to predict in-situ resistance degradation under vibration loads. However, these methods failed to capture the degradation trend under strong measurement noise. This paper introduces Monotonic Segmented Linear Regression (MSLR), a novel approach designed to capture monotonic degradation trends in time series data under significant measurement noise. By incorporating monotonic constraints, MSLR effectively models the non-decreasing behavior characteristic of degradation processes. To further enhance reliability of the prediction, we integrate Adaptive Conformal Inference (ACI) with MSLR, enabling the estimation of statistically valid upper bounds for resistance degradation with high confidence. Extensive experiments demonstrate that MSLR outperforms state-of-the-art time series forecasting baselines on real-world PCB degradation datasets.

Fan in and fan out wafer level packages are primarily used in the industry for applications in handheld consumer electronic products. The key benefits of wafer level package (WLP) are small form factor, reduced cost, improved electrical and thermal performance. WLP investigated in this study are directly surface mounted on PCB and have no intermediate substrate. Direct mount of package on PCB, leads to significant CTE mismatch between the package and board which stresses the package solder joint, leading to cyclic fatigue induced solder joint cracking. To overcome the solder joint cracking, stiffer solder alloys have been evaluated. However, higher stiffness of the solder alloy shifts the cyclic stress induced failure, from the solder joint to the package metal interconnect layers. Moreover, WLP on advanced silicon node have fragile low-k and extremely low-k back end of line dielectric layers that also crack or delaminate in cyclic fatigue. In this work extensive WLP platform development has been done with following DOE variables; multi-layer package routing, dielectric materials, die thickness, PCB design. Developed packages passed and outperformed the following product reliability qualification conditions - high temperature storage life (150°C, 1000 hours), highly accelerated stress test (110°C / 85%RH / Bias, 264 hours), component level temperature cycling (-55 °C to 125 °C, 1000 cycles), board level temperature cycling (-40 °C to 125 °C, 500 cycles) and board level drop test (1500g/0.5ms, 30 drops). Excellent reliability, functional performance, and successful chip package integration was achieved for WLP for crossover MCU products.

Board level reliability can be of high interest for automotive electronic components when exposed to vibration-prone environments. However, the absence of an industry standard for board level vibration testing poses several challenges in establishing a well-characterized test setup. One of the challenges is that automotive applications can induce abnormal stresses on components that can lead to early failures in the field. Such loading conditions are not always covered in the current board level vibration test methods. This paper aims to correlate the stresses from automotive modules to board levels by measuring the printed circuit board (PCB) vibration spectrum. Firstly, the study compares and assesses several module board level vibration measurement units, such as LASER Doppler Vibrometer (LDV), strain gauges, and accelerometers. Experiments and simulations show that LDV enables good correlation with Micro-electro Mechanical Systems (MEMS) accelerometers. Secondly, the module-board interaction unveils insights into several module design features that impact the PCB vibration response and solder joint interconnect reliability. These findings underscore the necessity for the user to correctly validate the reliability of packages beyond board level testing, i.e., at the module level. This reliability test approach enables the translation of reliability test results from the lab to the field life of components once built in the final application equipment.

Board level vibration testing is a commonly used method to predict the solder joint reliability of surface-mounted components seated onto printed circuit boards (PCB). Current board level vibration test methods are mainly developed from a solely mechanical stress application standpoint. This makes such stress tests one dimensional in nature and translation from experimentally obtained test results to the field life of components experiencing combined stress environments become ambiguous. This investigation provides insights to develop a highly accelerated vibration test approach to cover simultaneous vibration and temperature loading situations in the field. In this paper, test board layouts from the board level drop test method, JESD22-B111 (rectangular PCB), and JESD22-B111A (square PCB), prescribed by the Joint Electronic Device Engineering Council (JEDEC), are used to understand the combined stress applied to the solder interconnects. The evaluation process is carried out by means of simulations, supported by targeted experiments on ball grid array (BGA) packages with dimensions sizing from 12x12mm to 15x15mm. The results on rectangular test board assembly show reduced characteristic lifetime of solder joints when stressed under combined temperature-vibration test conditions. On the other hand, the square-shaped board type exhibits a different acceleration factor with a longer solder fatigue lifetime than that of the rectangular-shaped PCB type. Finite element simulation results complement well with this finding.

Board level vibration testing is intended to assess prediction of the reliability of solder joint interconnects that are formed between electronic components and printed circuit boards (PCB). Frailties in the stress test experiment might lead to false board level reliability (BLR) evaluations. Therefore, it is essential to have a well-characterized board level vibration test method. Currently, there is no industrial test standard that prescribes board level vibration test method for electronic components at the PCB level. This paper examines the vibration test standards that are currently available in the industry and their applicability at the solder joint interconnect level. Next to that, it surveys the state-of-the-art board level vibration test setups and their impact on PCB dynamic loading and reliability at solder joint-PCB interface. It collates research on major building blocks of a board level vibration test method that includes vibration measurement techniques, PCB assemblies under test, board mounting schemes, operating environments, fault detection systems, and vibration test stress conditions that are currently used in the domain of solder joint level vibration testing. The findings from this paper are expected to reveal pitfalls and challenges while setting up board level vibration test experiments for electronic components. In addition, this paper attempts to identify research efforts that are required to make board level vibration testing a more credible means for assessing solder joint reliability. Outcomes from this study can further be used to guide future board level vibration specifications for electronic components.