The three-step wet etching (TSWE) method has been proven to be a promising technique for fabricating silicon nanopores. Despite its potential, one of the bottlenecks of this method is the precise control of the silicon etching and etch-stop, which results in obtaining a well-defined nanopore size. Herein, we present a novel strategy leveraging electrochemical passivation to achieve accurate control over the silicon etching process. By dynamically controlling the oxide layer growth, rapid and reliable etch-stop was achieved in under 4 s, enabling the controllable fabrication of sub-10 nm silicon nanopores. The thickness of the oxide layer was precisely modulated by adjusting the passivation potential, achieving nanopore size shrinkage with a precision better than 2 nm, which can be further enhanced with more refined potential control. This scalable method significantly enhances the TSWE process, offering an efficient approach for producing small-size silicon nanopores with high precision. Importantly, the precise etching control facilitated by electrochemical passivation holds promise for the cost-effective production of high-density, air-insulated monolithic integrated circuits. (Figure presented.)

Van der Waals heterojunctions (vdWHs) have garnered significant attention for their promising applications in optoelectronics, attributed to their exceptional physical attributes. In this study, we present a straightforward approach to fabricating high-performance vdWHs photodetectors. Specifically, we prepared WSO_x/WS₂ vdWH photodetectors through the ozone oxidation of a WS₂ thin films at 100 °C. To characterize the morphology and optical properties of both the WS₂ and WSO_x/WS₂ thin films, we utilized atomic force microscopy (AFM) and Raman spectroscopy. Additionally, X-ray photoelectron spectroscopy (XPS) was employed to delve into the structural evolution by scrutinizing the bonding states of W, O, and S in the WS₂ before and after the ozone oxidation process. The resultant WSO_x/WS₂ vdWH photodetectors exhibited impressive photoelectric performance at wavelengths of 475 nm and 532 nm. It demonstrated a high responsivity of 230.7 A/W, a remarkable specific detectivity of 1.794 × 10¹¹ Jones, and a swift response speed of 60 ms at 475 nm. Furthermore, first-principles calculations based on density functional theory (DFT) were conducted to validate the oxidation kinetics of monolayer WS₂, the type II energy band alignment, and the interlayer charge transfer within the WSO_x/WS₂ vdWH. This research contributes novel insights into the synthesis of two-dimensional transition metal oxides (TMOs)-transition metal dichalcogenides (TMDCs) heterostructures for photodetector applications.

This article compares and evaluates the single pulse short-circuit robustness of silicon carbide (SiC) MOSFETs with linear and hexagonal cell topologies under different gate voltages, bus voltages, and case temperatures. The short-circuit failure mechanisms of the linear and hexagonal cell topologies are studied. A new switching model for gate failure and thermal runaway short-circuit failure modes is proposed and analyzed. The robustness performance of the linear and hexagonal cell topologies is compared and evaluated under the same short-circuit power for the first time, fully revealing the comprehensive impact mechanism of cell topologies on the short-circuit robustness for SiC MOSFETs.

Sintered Cu nanoparticles (NPs) are promising for high-performance electronics due to their excellent thermal and electrical conductivity, as well as mechanical reliability. This study investigates the microscale mechanical behavior of sintered Cu NPs with a bimodal particle size distribution, focusing on strain rate and temperature effects. Micro-pillar compression tests were performed across strain rates of 0.0001 s⁻¹ to 0.01 s⁻¹ and temperatures from 25 °C to 350 °C. Results show that higher strain rates enhance yield strength through strain-rate hardening, while elevated temperatures lead to thermal softening and reduced mechanical stability. The Anand viscoplastic model accurately predicts these deformation behaviors. Microstructural analysis via scanning electron microscopy (SEM) and transmission electron microscopy (TEM) reveals localized deformation at 175 °C, with dislocations concentrated near the top surface and persistent porosity below, whereas at 350 °C, re-sintering and grain boundary diffusion create a denser microstructure. Phase-field fracture modeling further elucidates crack propagation, emphasizing the role of pore size and temperature. This combined experimental and modeling approach enhances understanding of viscoplastic deformation and fracture mechanisms in sintered Cu NPs, informing their use in interconnects, power electronics and thermal management systems.

This paper investigates the effects of three ageing factors (chemical, humidity, and temperature) and their interactions on the physical properties and degradation of silicone sealant used in microelectronic applications. The thermal degradation of silicone sealants was investigated by exposing samples to temperatures in the range of 150 up to 175 °C. Also, a set of samples were aged at 40 °C in a salt spray set-up with 100 % humidity in a salty atmosphere. Results showed detectable changes in the FTIR spectra of aged specimen as compared with the as-received sample. In all accelerated testing conditions, peak intensities decreased with ageing time, inferring that that the surface characteristics of the sealant is affected by ageing. Shear test results showed that with increasing the ageing time, the maximum shear stress in most cases has decreased in all ageing conditions. Also, it appears that samples with longer ageing times have experienced more elongation before failure. Results also show that salt spraying of specimens is associated with a decrease in the mechanical properties of the sealant, indicating the deleterious implications of ionic contaminations for the mechanical properties of samples.

This Letter presents a combined analytical and experimental method to effectively decouple the radial and tangential residual stress fields induced by Berkovich nanoindentation in single-crystalline 4H-SiC using micro-Raman spectroscopy. By integrating the Raman stress characterization model with Yoffe’s expanding cavity model, precise extraction of individual residual stress components around the indentation region is realized. Through the vertical backscattering micro-Raman mapping of the E2 phonon mode, we systematically investigate the residual stress distribution near the indentation. The results highlight significant anisotropy in nanoindentation-induced stress fields, strongly dependent on the crystal orientation of 4H-SiC, predominantly featuring radial tensile stress gradients. This comprehensive theoretical–experimental approach offers a robust optical framework for residual stress characterization in 4H-SiC and provides foundational insights for extending Raman spectroscopy-based stress characterization to other crystalline materials and related device structures.

In this study, we introduced a hybrid Potts-phase field model to simulate the co-evolution of grain growth and pores migration in sintered silver layers. The Potts model is good at capture the grain growth dynamics, while the phase field model describes the evolution of the porous network. These models are coupled via a hybrid free energy function to achieve a realistic representation of the microstructure evolution. This study further extends the hybrid model by incorporating (a) a flexible exchange interaction matrix to model the crystal anisotropy in grain growth, (b) Glauber or Kawasaki dynamics to describe different diffusion mechanisms, and (c) the effect of pinning sites, representing impurity-driven grain boundary stabilization. The computational framework is implemented using Taichi Lang, which allows for efficient parallel simulations. Results show that the model effectively captures the long-term evolution of the sintered silver microstructure in good agreement with experimental observations. This hybrid model is a powerful tool to predict microstructural reliability of sintered silver die attach layers, supporting material design and process optimization for high-power electronic applications.

This study investigates the interface strength and fracture behavior of sintered copper (Cu) nanoparticles (NPs) for all-Cu integration in advanced microelectronics packaging. Micro-cantilever bending tests on three configurations (Cu NP-notched, interface-notched and un-notched micro-cantilevers) were analyzed using scanning electron microscopy (SEM), transmission electron microscopy (TEM), transmission Kikuchi diffraction (TKD) and cohesive zone model (CZM). The interface-notched micro-cantilevers demonstrate superior fracture resistance, with a stress intensity factor (K_Q) of 2.88±0.10 MPa m^1/2, compared to 2.12±0.11 MPa m^1/2 for Cu NP-notched micro-cantilevers. Simulation results, consistent with experimental results, reveal that Cu NP-notched micro-cantilevers exhibit lower fracture resistance due to porosity and stress concentrations, while interface-notched micro-cantilevers show enhanced strength, attributed to robust bonding and reduced void distribution. Un-notched micro-cantilevers display superior load-bearing capacity, with cracks bypassing the interface and propagating through porous regions. Moreover, in un-notched micro-cantilevers, a synergistic deformation mechanism is observed, where crack propagation through the sintered Cu NPs coexists with plastic slip deformation in the Cu substrate. These findings highlight the strong interfacial bonding and effective stress transfer at the Cu substrate-sintered Cu NP interface, validating the feasibility of direct sintering using Cu NPs without additional coatings.

The heat produced within the device in its package depends on the power supplied to each IP block. The improper placement of an IP block with high power consumption can become a reliability risk for IC packages, as it can significantly affect the reliability of solder balls due to thermal, mechanical, and electrical factors. It also mitigates the effect of thermal cycling, because it depends upon heat management within the package. Improper IP block placement can block heat flow paths, which results in poor thermal dissipation and higher temperature which can create a higher strain on the solder balls affecting their lifetime. Therefore, it is crucial to understand the interplay between the correct placement of IP blocks and solder balls to enhance solder ball reliability. COMSOL-based simulation study will be done on a WLCSP (Wafer Level Chip Scale Package) mounted on a PCB board on which solder balls are connected to copper layers on the die and PCB sides. Variations in the placement of the IP blocks. Thermal cycling and the variations in the placement of the IP block within the package will be taken as a loading condition. Therefore, this influences the susceptibility of device failure due to solder ball fatigue. Based on board-level passive cycling, the solder balls which are located under the IP blocks are the most likely ones affected by this stress. The results will be analyzed to optimize the layout of the IP blocks, concerning accumulated plastic strain on the solder balls at different locations of the IP block placement. It can help to understand the influence of the position of the IP block, reduce stress concentration, and minimize thermal cycling effects, which leads to an increase in the reliability of the solders joint and IC package itself.

This article presents a novel in-package relative humidity (RH) sensor designed to enhance moisture detection within the chip encapsulation material, specifically epoxy molding compound (EMC). Traditional methods for assessing EMC moisture content, such as mass measurements, are time-consuming and incompatible with industrial reliability tests, limiting their use for real-time, in situ monitoring. To address these challenges, we propose an integrated capacitive sensor that directly measures moisture content within the encapsulation material. The sensor utilizes a heterogeneous electrode design to overcome the sensitivity limitations of conventional interdigital electrodes (IDEs). This design features sections of different widths, allowing selective wet chemical etching of the silicon dioxide layer using buffered hydrofluoric acid (BHF). By controlling the etching time, the silicon dioxide layer beneath the narrower sections is completely etched, while oxide pillars form under the wider sections, resulting in semifloating electrodes. The EMC fills the etched regions and wraps around the narrower sections, concentrating more electric field lines in the EMC and enhancing sensor sensitivity. Our proposed sensor achieves a capacitance change of 1 pF per 80% RH, improving sensitivity from 6.9 to 12.3 fF/%RH, with a 20% increase in relative capacitance change. A shielding layer is added to minimize parasitic capacitance effects, ensuring accurate measurements. The proposed sensor is fully CMOS-compatible and can monitor moisture-induced reliability risks, as well as assess packaging material aging. This work provides a cost-effective and reliable solution for in-package humidity monitoring in semiconductor applications.

The mechanical strength of sintered nanoparticles (NPs) limits their application in advanced electronics packaging. In this study, we explore the anisotropy in the microstructure and mechanical properties of sintered copper (Cu) NPs by combining experimental techniques with molecular dynamics (MD) simulations. We establish a clear relationship between processing conditions, microstructural evolution, and resulting properties in pressure-assisted sintering of Cu NPs. Our findings reveal that pressure-assisted sintering induces significant anisotropy in the microstructure, as evidenced by variations in areal relative density and the orientation distribution of necks formed during sintering. Specifically, along the direction of applied pressure, the microstructure exhibits reduced variation in areal relative density and a higher prevalence of necks with favorable orientations. The resulting anisotropic mechanical properties, with significantly higher strength along the pressure direction compared to other directions, are demonstrated through micro-cantilever bending tests and tensile simulations. This anisotropy is further explained by the combined effects of strain localization (influenced by areal relative density) and the failure modes of necks (determined by their orientation relative to the loading direction). This work provides valuable insights into the analysis of sintered NPs microstructures and offers guidance for optimizing the sintering process.

The use of microRNAs as clinical cancer biomarkers is hindered by the absence of accurate, sensitive and rapid assays for their detection in biofluids. Here we report a biosensing approach, SpLig-HEMT, that combines an RNA splint-ligation reaction with an AlGaN/GaN high-electron-mobility transistor biosensor for ultrasensitive miRNA detection. In this system, HEMT functions as a highly effective voltage amplifier to enhance detection sensitivity, while the splint-ligation reaction ensures precise discrimination of single-nucleotide mutations. By detecting miRNA-21, the SpLig-HEMT biosensor achieves an exceptional limit of detection of 10⁻¹⁸ M within 30 min, with a dynamic range from 10⁻¹⁸ M to 10⁻¹³ M. No detectable response is observed for one-mismatch miR-21. Furthermore, the SpLig-HEMT biosensor enables direct analysis of blood serum samples, effectively distinguishing between healthy individuals and patients with ovarian cancer. This study addresses critical challenges in miRNA detection and presents a promising tool for cancer diagnosis and prognosis.

Power electronics devices, pivotal in advancing electronic system technology, are essential for energy saving, enhancing power control efficiency, reducing noise, and minimizing size and volume. The evolution of power modules is based on innovative packaging structures, technologies, and materials. This article provides a comprehensive review of inorganic nonmetallic packaging materials and technologies in power electronics packaging. It first analyzes the packaging structures and trends of power electronics. The article then discusses inorganic nonmetallic encapsulants such as cement and glass in detail. It also reviews traditional ceramic substrates and elaborates on the advantages of multilayer ceramic technologies, including low-temperature co-fired ceramics, as substrates, while looking forward to the commercialization of inorganic composite substrates such as SiCp/Al matrix composites and diamond. Subsequently, the article overviews inorganic nonmetallic fillers for thermal interface materials, emphasizing the application of two-dimensional materials such as graphene and boron nitride, and introduces inorganic nonmetallic phase change materials. Finally, it explores the application and future development trends of inorganic nonmetallic materials in embedded packaging technologies.

This study investigates the size-dependent mechanical behavior and deformation mechanisms of sintered copper (Cu) nanoparticles (NPs) through micro-pillar (2–6 μm diameter) compression tests, scanning electron microscopy (SEM), transmission electron microscopy (TEM), transmission Kikuchi diffraction (TKD) analysis and molecular dynamics (MD) simulations. In-situ micro-pillar compression tests reveal a 25.9% reduction in yield strength (812 ± 64 MPa to 643 ± 47 MPa) with increasing pillar size, attributed to dislocation starvation in smaller pillars and porosity-driven strain localization in larger ones. TKD quantifies dynamic grain refinement (24.9% reduction in grain size) and geometrically necessary dislocation (GND) density escalation (74.8%), driven by stress gradients and grain boundary-mediated plasticity. Nanoindentation-derived elastic modulus (48.3 ± 11.1 GPa) exceeds micropillar values (29.5–33.9 GPa), reflecting substrate constraints in bulk testing. Microstructural analysis identifies a transition from shear banding in high-porosity pillars to uniform plasticity in denser systems, mediated by texture evolution (Brass/S components) and Schmid factor redistribution (62% increase in high-slip-activity grains). MD simulations of pressure-sintered Cu NPs elucidate atomic-scale mechanisms: dislocation nucleation at sintering necks, pore collapse-induced strain localization, and grain boundary sliding. These findings establish a multiscale framework linking porosity, grain refinement, and dislocation dynamics to mechanical performance, emphasizing microstructural optimization for enhanced reliability in microelectronic applications. The integration of MD simulations bridges atomic-scale mechanisms to microscale deformation, providing actionable insights for tailoring sintered Cu NPs via reduced porosity and controlled grain boundary architectures.

The 1.2 kV SiC VDMOSFETs with varied JFET width (LJFET) are designed and fabricated in this study. The static and dynamic characteristics of each design are measured and compared. There is the best trade-off performance in the design of LJFET = 1.8 μm according to FOM (BV2/Ron) and FOM (Ciss/Crss). Besides, the surge capacity and evaluation for series designs are investigated under conditions of Vgs = 0 V and Vgs = −5 V. There is a best surge capacity in design of LJFET=1.2 μm, and the largest surge energy is the design of LJFET=2.0 μm. Further, the surge failure mechanisms of LJFET = 1.2 μm, 1.8 μm, and 2.0 μm under condition of Vgs = −5 V are investigated by decapsulated and FIB. Besides, the TCAD simulation was employed to theoretical analysis. The results show that the extremely high temperature was generated instantaneously under surge condition, resulting in epoxy carbonization, polysilicon melting and ILD oxide crack in failed position. Besides, the surge dissipating energy causes an instantaneous high temperature on the entire chip, resulting in aluminum remetallization. This paper would provide suggestions for device design and surge study.

The degradation mechanisms of silicon carbide (SiC) VDMOSFET and trench metal oxide semiconductor field effect transistor (MOSFET) in a 60Co gamma irradiation environment were investigated. The degradation of electrical characteristics of SiC MOSFET in different working states after irradiation with different total ionizing doses (TIDs) was explored. The defects induced during the irradiation process were studied in annealing experiments conducted after irradiation. The reasons for the degradation of SiC MOSFET caused by TID were revealed, and a prediction model of threshold voltage (Vth) shift was proposed and verified through TCAD simulation. The Vth, breakdown voltage (BV), on-resistance R, input capacitance (Ciss), output capacitance Coss, and reverse transfer capacitance C _rss were measured at different irradiation doses and annealing conditions. Experimental results indicated that the degradation of both Ron and Ciss was primarily caused by the Vth shift. As the doses increased, the shift in Vth gradually reached saturation. Similar trends to VDMOSFET were observed in trench MOSFET but with greater sensitivity to TID. In addition, MOSFETs biased at zero voltage exhibited lower shifts in Vth compared with those under high gate bias conditions. Furthermore, the increase in defects in the gate oxide during irradiation and annealing processes were calculated. Finally, a model predicting Vth shift path was established, and its accuracy and limitations were determined. This study provides valuable insights into the effect of TID on SiC MOSFETs.

Sintered materials have been widely applied, as an alternative to soldering, for power electronics packaging. One key issue for such die-attach material is to characterize the actual porosity, which is difficult to obtain through SEM cross-section analysis. Therefore, in this work, the optimized Quartet Structure Generation Set (QSGS) algorithm was applied to sintered copper joints under various porosity levels to reconstruct 3D porous structures based on 2D SEM images. Firstly, copper joints with varying porosities were fabricated under different sintering conditions. Reconstructed 3D porous copper models were then generated through the QSGS algorithm to match experimental observations, including porosity and pore size. Finite element analysis (FEA) simulations were further conducted to explore the effects of pores on thermal and electrical performance. This work provides a method for accurately predicting the thermoelectric properties of sintered copper joints and insights for optimizing copper sintering in power electronics applications.

Triboelectric nanogenerator (TENG), advantageous in high energy density and flexibility, is promising as a sustainable energy source but can hardly be used to power edge devices directly due to its high-voltage AC output and varying capacitive impedance. To address it, this work proposes a power-conditioning interface with a fully integrated dual synchronous switch harvesting on capacitors (D-SSHC) rectifier for triboelectric energy extraction. Furthermore, a full digital duty-cycle-based (DCB) maximum power point tracking (MPPT) algorithm is developed to optimize the energy harvesting efficiency with simple implementation and continuous tracking. Designed and fabricated in a 0.18-μm BCD process, the proposed interface can extract energy at a maximum output voltage of 70 V. According to the measurement results, it achieves 99% MPPT efficiency and an energy extraction improvement of 598% compared to a full-bridge rectifier.

This study presents a novel approach for localized silver (Ag) nanoparticles (NPs) sintering using microheater arrays embedded within the Si substrate. By applying controlled pulse currents, these microheaters generate targeted heat pulses, enabling rapid and localized sintering while maintaining the surrounding device components at room temperature. This localized heating minimizes thermal stress caused by thermal expansion mismatches, as sintering completes within milliseconds. Compared to conventional sintering techniques, this method improves process efficiency, reduces power consumption, and provides precise spatial control over the sintered regions. The proposed approach offers a promising alternative for microelectronics packaging and integration, particularly in applications requiring precise thermal management.

Graphdiyne (GDY)/two-dimensional materials (2DMs) heterostructures present unique opportunities for advanced optoelectronic and neuromorphic devices because of their exceptional electrical, optical, and structural properties. However, the traditional methods for construction of GDY/2DMs heterostructures usually lead to inferior interfaces, which seriously affects the charge separation and transport. Herein, an in situ approach for growing GDY nanowalls (NWs) on WSe2 is employed in this work. The as-prepared GDY NWs/WSe2 heterostructure exhibits self-powered broadband photodetection across 405–980 nm with a high responsivity of 2176 A/W and detectivity of 3.6 × 1012 Jones at 532 nm under 0.02 mW/cm2 illumination, significantly outperforming previously reported GDY-based devices. The efficient charge separation and strong photocarrier trapping in the GDY NWs/WSe2 heterostructure result in pronounced short-term and long-term synaptic plasticity. The nonlinear, wavelength-dependent reservoir state separation enables clear distinction of multiple pulse sequences, which shows great potential for logic processing. The successfully resolved red, green, and violet patterns, and one-shot color image recognition of a 5-letter image highlight transformative potential of GDY NWs/WSe2 device for future adaptive imaging and neuromorphic computing technologies.