The 1.2 kV SiC VDMOSFETs with varied JFET width (LJFET) are designed and fabricated in this study. The static and dynamic characteristics of each design are measured and compared. There is the best trade-off performance in the design of LJFET = 1.8 μm according to FOM (BV2/Ron) and FOM (Ciss/Crss). Besides, the surge capacity and evaluation for series designs are investigated under conditions of Vgs = 0 V and Vgs = −5 V. There is a best surge capacity in design of LJFET=1.2 μm, and the largest surge energy is the design of LJFET=2.0 μm. Further, the surge failure mechanisms of LJFET = 1.2 μm, 1.8 μm, and 2.0 μm under condition of Vgs = −5 V are investigated by decapsulated and FIB. Besides, the TCAD simulation was employed to theoretical analysis. The results show that the extremely high temperature was generated instantaneously under surge condition, resulting in epoxy carbonization, polysilicon melting and ILD oxide crack in failed position. Besides, the surge dissipating energy causes an instantaneous high temperature on the entire chip, resulting in aluminum remetallization. This paper would provide suggestions for device design and surge study.

Van der Waals heterojunctions (vdWHs) have garnered significant attention for their promising applications in optoelectronics, attributed to their exceptional physical attributes. In this study, we present a straightforward approach to fabricating high-performance vdWHs photodetectors. Specifically, we prepared WSO_x/WS₂ vdWH photodetectors through the ozone oxidation of a WS₂ thin films at 100 °C. To characterize the morphology and optical properties of both the WS₂ and WSO_x/WS₂ thin films, we utilized atomic force microscopy (AFM) and Raman spectroscopy. Additionally, X-ray photoelectron spectroscopy (XPS) was employed to delve into the structural evolution by scrutinizing the bonding states of W, O, and S in the WS₂ before and after the ozone oxidation process. The resultant WSO_x/WS₂ vdWH photodetectors exhibited impressive photoelectric performance at wavelengths of 475 nm and 532 nm. It demonstrated a high responsivity of 230.7 A/W, a remarkable specific detectivity of 1.794 × 10¹¹ Jones, and a swift response speed of 60 ms at 475 nm. Furthermore, first-principles calculations based on density functional theory (DFT) were conducted to validate the oxidation kinetics of monolayer WS₂, the type II energy band alignment, and the interlayer charge transfer within the WSO_x/WS₂ vdWH. This research contributes novel insights into the synthesis of two-dimensional transition metal oxides (TMOs)-transition metal dichalcogenides (TMDCs) heterostructures for photodetector applications.

Graphdiyne (GDY)/two-dimensional materials (2DMs) heterostructures present unique opportunities for advanced optoelectronic and neuromorphic devices because of their exceptional electrical, optical, and structural properties. However, the traditional methods for construction of GDY/2DMs heterostructures usually lead to inferior interfaces, which seriously affects the charge separation and transport. Herein, an in situ approach for growing GDY nanowalls (NWs) on WSe2 is employed in this work. The as-prepared GDY NWs/WSe2 heterostructure exhibits self-powered broadband photodetection across 405–980 nm with a high responsivity of 2176 A/W and detectivity of 3.6 × 1012 Jones at 532 nm under 0.02 mW/cm2 illumination, significantly outperforming previously reported GDY-based devices. The efficient charge separation and strong photocarrier trapping in the GDY NWs/WSe2 heterostructure result in pronounced short-term and long-term synaptic plasticity. The nonlinear, wavelength-dependent reservoir state separation enables clear distinction of multiple pulse sequences, which shows great potential for logic processing. The successfully resolved red, green, and violet patterns, and one-shot color image recognition of a 5-letter image highlight transformative potential of GDY NWs/WSe2 device for future adaptive imaging and neuromorphic computing technologies.

Sintered materials have been widely applied, as an alternative to soldering, for power electronics packaging. One key issue for such die-attach material is to characterize the actual porosity, which is difficult to obtain through SEM cross-section analysis. Therefore, in this work, the optimized Quartet Structure Generation Set (QSGS) algorithm was applied to sintered copper joints under various porosity levels to reconstruct 3D porous structures based on 2D SEM images. Firstly, copper joints with varying porosities were fabricated under different sintering conditions. Reconstructed 3D porous copper models were then generated through the QSGS algorithm to match experimental observations, including porosity and pore size. Finite element analysis (FEA) simulations were further conducted to explore the effects of pores on thermal and electrical performance. This work provides a method for accurately predicting the thermoelectric properties of sintered copper joints and insights for optimizing copper sintering in power electronics applications.

The study focuses on the optical and electrical properties of Tungsten Ditelluride (WTe2), a type II Weyl semimetal, as well as the influence of its self-limiting oxide (SLO) layer that forms during natural oxidation. WTe2 exhibits promising applications in photodetection and energy harvesting due to its unique gapless linear dispersion and Berry-field-enhanced nonlinear optical effects. However, surface oxidation poses a challenge as it degrades the performance of WTe2. By employing spectroscopic ellipsometry and Raman spectroscopy, the progression of the oxide layer’s thickness and its impact on the optical constants of WTe2 were examined. The results revealed a rapid increase in oxide thickness within the first 24 h, and it reached saturation at ∼10 nm after 45 h of atmospheric exposure. Electrical properties were explored using Kelvin Probe Force Microscopy, uncovering a modification in surface potential and Fermi level following oxidation. Additionally, a SLO/WTe2 heterojunction device exhibited a wide region of positive and negative coexisting photocurrent, highlighting the potential for logical operations in ambient air. Finally, the mechanism of operation of the device is discussed. The electrical and optical properties of the pristine, partially oxidized and fully oxidized WTe2 are analyzed using density functional theory calculations. It shows that the SLO layer has a significant effect on the optical and electronic properties, which is instructive for future wavelength-modulated device optoelectronic logic operations.

This study investigates the size-dependent mechanical behavior and deformation mechanisms of sintered copper (Cu) nanoparticles (NPs) through micro-pillar (2–6 μm diameter) compression tests, scanning electron microscopy (SEM), transmission electron microscopy (TEM), transmission Kikuchi diffraction (TKD) analysis and molecular dynamics (MD) simulations. In-situ micro-pillar compression tests reveal a 25.9% reduction in yield strength (812 ± 64 MPa to 643 ± 47 MPa) with increasing pillar size, attributed to dislocation starvation in smaller pillars and porosity-driven strain localization in larger ones. TKD quantifies dynamic grain refinement (24.9% reduction in grain size) and geometrically necessary dislocation (GND) density escalation (74.8%), driven by stress gradients and grain boundary-mediated plasticity. Nanoindentation-derived elastic modulus (48.3 ± 11.1 GPa) exceeds micropillar values (29.5–33.9 GPa), reflecting substrate constraints in bulk testing. Microstructural analysis identifies a transition from shear banding in high-porosity pillars to uniform plasticity in denser systems, mediated by texture evolution (Brass/S components) and Schmid factor redistribution (62% increase in high-slip-activity grains). MD simulations of pressure-sintered Cu NPs elucidate atomic-scale mechanisms: dislocation nucleation at sintering necks, pore collapse-induced strain localization, and grain boundary sliding. These findings establish a multiscale framework linking porosity, grain refinement, and dislocation dynamics to mechanical performance, emphasizing microstructural optimization for enhanced reliability in microelectronic applications. The integration of MD simulations bridges atomic-scale mechanisms to microscale deformation, providing actionable insights for tailoring sintered Cu NPs via reduced porosity and controlled grain boundary architectures.

High-energy Al ion implantation is an indispensable technique for achieving precise doping in fabricating 4H‑SiC devices. However, it inevitably introduces interfacial damage and residual stress that can compromise subsequent manufacturing processes and device reliability. Conventional destructive characterization techniques cannot provide real-time, in‑situ, nondestructive monitoring under process conditions, creating a major bottleneck in quality control. Here, we establish a predictive modeling framework that integrates multiscale simulations with advanced, non‑destructive micro‑Raman spectroscopy to systematically investigate the evolution of high-energy Al ion implantation–induced interface defects and residual stress in 4H-SiC. Simulation results reveal a linear relationship between the implantation dose and the formation of vacancies and interstitial defects, while the stress accumulation tends to saturate at higher doses due to a dynamic equilibrium among defect interactions. Complementary micro‐Raman spectroscopy corroborates the simulations, showing that the damaged interface layer deepens from approximately 300 nm at a dose of 1014 ions cm−2 to nearly 500 nm at 1016 ions cm−2, consistent with Monte Carlo predictions. Furthermore, the molecular dynamics simulations capture a trend of the implantation stress evolution with strong concurrence with the Raman-measured residual stress. This combined computational–experimental approach elucidates the fundamental mechanisms governing defect formation and residual stress in ion‑implanted 4H‑SiC, establishes implantation dose as the pivotal role of 4H-SiC in defect density and residual stress, and underscores the utility of optical‑based characterization in real‑time, non‑invasive quality control for advanced manufacturing.

This paper investigates the effects of three ageing factors (chemical, humidity, and temperature) and their interactions on the physical properties and degradation of silicone sealant used in microelectronic applications. The thermal degradation of silicone sealants was investigated by exposing samples to temperatures in the range of 150 up to 175 °C. Also, a set of samples were aged at 40 °C in a salt spray set-up with 100 % humidity in a salty atmosphere. Results showed detectable changes in the FTIR spectra of aged specimen as compared with the as-received sample. In all accelerated testing conditions, peak intensities decreased with ageing time, inferring that that the surface characteristics of the sealant is affected by ageing. Shear test results showed that with increasing the ageing time, the maximum shear stress in most cases has decreased in all ageing conditions. Also, it appears that samples with longer ageing times have experienced more elongation before failure. Results also show that salt spraying of specimens is associated with a decrease in the mechanical properties of the sealant, indicating the deleterious implications of ionic contaminations for the mechanical properties of samples.

This article compares and evaluates the single pulse short-circuit robustness of silicon carbide (SiC) MOSFETs with linear and hexagonal cell topologies under different gate voltages, bus voltages, and case temperatures. The short-circuit failure mechanisms of the linear and hexagonal cell topologies are studied. A new switching model for gate failure and thermal runaway short-circuit failure modes is proposed and analyzed. The robustness performance of the linear and hexagonal cell topologies is compared and evaluated under the same short-circuit power for the first time, fully revealing the comprehensive impact mechanism of cell topologies on the short-circuit robustness for SiC MOSFETs.

The three-step wet etching (TSWE) method has been proven to be a promising technique for fabricating silicon nanopores. Despite its potential, one of the bottlenecks of this method is the precise control of the silicon etching and etch-stop, which results in obtaining a well-defined nanopore size. Herein, we present a novel strategy leveraging electrochemical passivation to achieve accurate control over the silicon etching process. By dynamically controlling the oxide layer growth, rapid and reliable etch-stop was achieved in under 4 s, enabling the controllable fabrication of sub-10 nm silicon nanopores. The thickness of the oxide layer was precisely modulated by adjusting the passivation potential, achieving nanopore size shrinkage with a precision better than 2 nm, which can be further enhanced with more refined potential control. This scalable method significantly enhances the TSWE process, offering an efficient approach for producing small-size silicon nanopores with high precision. Importantly, the precise etching control facilitated by electrochemical passivation holds promise for the cost-effective production of high-density, air-insulated monolithic integrated circuits. (Figure presented.)

The use of microRNAs as clinical cancer biomarkers is hindered by the absence of accurate, sensitive and rapid assays for their detection in biofluids. Here we report a biosensing approach, SpLig-HEMT, that combines an RNA splint-ligation reaction with an AlGaN/GaN high-electron-mobility transistor biosensor for ultrasensitive miRNA detection. In this system, HEMT functions as a highly effective voltage amplifier to enhance detection sensitivity, while the splint-ligation reaction ensures precise discrimination of single-nucleotide mutations. By detecting miRNA-21, the SpLig-HEMT biosensor achieves an exceptional limit of detection of 10⁻¹⁸ M within 30 min, with a dynamic range from 10⁻¹⁸ M to 10⁻¹³ M. No detectable response is observed for one-mismatch miR-21. Furthermore, the SpLig-HEMT biosensor enables direct analysis of blood serum samples, effectively distinguishing between healthy individuals and patients with ovarian cancer. This study addresses critical challenges in miRNA detection and presents a promising tool for cancer diagnosis and prognosis.

Power electronics devices, pivotal in advancing electronic system technology, are essential for energy saving, enhancing power control efficiency, reducing noise, and minimizing size and volume. The evolution of power modules is based on innovative packaging structures, technologies, and materials. This article provides a comprehensive review of inorganic nonmetallic packaging materials and technologies in power electronics packaging. It first analyzes the packaging structures and trends of power electronics. The article then discusses inorganic nonmetallic encapsulants such as cement and glass in detail. It also reviews traditional ceramic substrates and elaborates on the advantages of multilayer ceramic technologies, including low-temperature co-fired ceramics, as substrates, while looking forward to the commercialization of inorganic composite substrates such as SiCp/Al matrix composites and diamond. Subsequently, the article overviews inorganic nonmetallic fillers for thermal interface materials, emphasizing the application of two-dimensional materials such as graphene and boron nitride, and introduces inorganic nonmetallic phase change materials. Finally, it explores the application and future development trends of inorganic nonmetallic materials in embedded packaging technologies.

In this study, we introduced a hybrid Potts-phase field model to simulate the co-evolution of grain growth and pores migration in sintered silver layers. The Potts model is good at capture the grain growth dynamics, while the phase field model describes the evolution of the porous network. These models are coupled via a hybrid free energy function to achieve a realistic representation of the microstructure evolution. This study further extends the hybrid model by incorporating (a) a flexible exchange interaction matrix to model the crystal anisotropy in grain growth, (b) Glauber or Kawasaki dynamics to describe different diffusion mechanisms, and (c) the effect of pinning sites, representing impurity-driven grain boundary stabilization. The computational framework is implemented using Taichi Lang, which allows for efficient parallel simulations. Results show that the model effectively captures the long-term evolution of the sintered silver microstructure in good agreement with experimental observations. This hybrid model is a powerful tool to predict microstructural reliability of sintered silver die attach layers, supporting material design and process optimization for high-power electronic applications.

The heat produced within the device in its package depends on the power supplied to each IP block. The improper placement of an IP block with high power consumption can become a reliability risk for IC packages, as it can significantly affect the reliability of solder balls due to thermal, mechanical, and electrical factors. It also mitigates the effect of thermal cycling, because it depends upon heat management within the package. Improper IP block placement can block heat flow paths, which results in poor thermal dissipation and higher temperature which can create a higher strain on the solder balls affecting their lifetime. Therefore, it is crucial to understand the interplay between the correct placement of IP blocks and solder balls to enhance solder ball reliability. COMSOL-based simulation study will be done on a WLCSP (Wafer Level Chip Scale Package) mounted on a PCB board on which solder balls are connected to copper layers on the die and PCB sides. Variations in the placement of the IP blocks. Thermal cycling and the variations in the placement of the IP block within the package will be taken as a loading condition. Therefore, this influences the susceptibility of device failure due to solder ball fatigue. Based on board-level passive cycling, the solder balls which are located under the IP blocks are the most likely ones affected by this stress. The results will be analyzed to optimize the layout of the IP blocks, concerning accumulated plastic strain on the solder balls at different locations of the IP block placement. It can help to understand the influence of the position of the IP block, reduce stress concentration, and minimize thermal cycling effects, which leads to an increase in the reliability of the solders joint and IC package itself.

This study presents a novel approach for localized silver (Ag) nanoparticles (NPs) sintering using microheater arrays embedded within the Si substrate. By applying controlled pulse currents, these microheaters generate targeted heat pulses, enabling rapid and localized sintering while maintaining the surrounding device components at room temperature. This localized heating minimizes thermal stress caused by thermal expansion mismatches, as sintering completes within milliseconds. Compared to conventional sintering techniques, this method improves process efficiency, reduces power consumption, and provides precise spatial control over the sintered regions. The proposed approach offers a promising alternative for microelectronics packaging and integration, particularly in applications requiring precise thermal management.

The mechanical strength of sintered nanoparticles (NPs) limits their application in advanced electronics packaging. In this study, we explore the anisotropy in the microstructure and mechanical properties of sintered copper (Cu) NPs by combining experimental techniques with molecular dynamics (MD) simulations. We establish a clear relationship between processing conditions, microstructural evolution, and resulting properties in pressure-assisted sintering of Cu NPs. Our findings reveal that pressure-assisted sintering induces significant anisotropy in the microstructure, as evidenced by variations in areal relative density and the orientation distribution of necks formed during sintering. Specifically, along the direction of applied pressure, the microstructure exhibits reduced variation in areal relative density and a higher prevalence of necks with favorable orientations. The resulting anisotropic mechanical properties, with significantly higher strength along the pressure direction compared to other directions, are demonstrated through micro-cantilever bending tests and tensile simulations. This anisotropy is further explained by the combined effects of strain localization (influenced by areal relative density) and the failure modes of necks (determined by their orientation relative to the loading direction). This work provides valuable insights into the analysis of sintered NPs microstructures and offers guidance for optimizing the sintering process.

Optical micro-electromechanical systems (MEMS) demand exceptional precision, yet warpage during the die attach process on printed circuit boards can compromise performance. Here, a three-dimensional thermoelastic analytical model has been developed based on Fourier heat conduction and supported beam theory. This model facilitates the in-situ calibration of solder parameters via confocal micro-Raman spectroscopy, ensuring that the simulated dynamic evolution of warpage during soldering aligns closely with digital image correlation experiments. The results show consistence with Finite Element Method with error less than 1 % and time saving more than 60 %. Orthogonal experimental analysis further reveals that substrate thickness and thermal expansion coefficient variations are the primary factors affecting warpage, while chip area has a negligible role. Given the practical challenges in reducing substrate thickness, a stress-balancing strategy incorporating an additional transition layer is proposed, which is effectively validated with a high-resolution three-dimensional profilometer. This work provides valuable insights into the predictive modeling and warpage behavior characterization, directly supporting improved mitigation strategies in the die attach process.

Sintered Cu nanoparticles (NPs) are promising for high-performance electronics due to their excellent thermal and electrical conductivity, as well as mechanical reliability. This study investigates the microscale mechanical behavior of sintered Cu NPs with a bimodal particle size distribution, focusing on strain rate and temperature effects. Micro-pillar compression tests were performed across strain rates of 0.0001 s⁻¹ to 0.01 s⁻¹ and temperatures from 25 °C to 350 °C. Results show that higher strain rates enhance yield strength through strain-rate hardening, while elevated temperatures lead to thermal softening and reduced mechanical stability. The Anand viscoplastic model accurately predicts these deformation behaviors. Microstructural analysis via scanning electron microscopy (SEM) and transmission electron microscopy (TEM) reveals localized deformation at 175 °C, with dislocations concentrated near the top surface and persistent porosity below, whereas at 350 °C, re-sintering and grain boundary diffusion create a denser microstructure. Phase-field fracture modeling further elucidates crack propagation, emphasizing the role of pore size and temperature. This combined experimental and modeling approach enhances understanding of viscoplastic deformation and fracture mechanisms in sintered Cu NPs, informing their use in interconnects, power electronics and thermal management systems.

This study investigates the interface strength and fracture behavior of sintered copper (Cu) nanoparticles (NPs) for all-Cu integration in advanced microelectronics packaging. Micro-cantilever bending tests on three configurations (Cu NP-notched, interface-notched and un-notched micro-cantilevers) were analyzed using scanning electron microscopy (SEM), transmission electron microscopy (TEM), transmission Kikuchi diffraction (TKD) and cohesive zone model (CZM). The interface-notched micro-cantilevers demonstrate superior fracture resistance, with a stress intensity factor (K_Q) of 2.88±0.10 MPa m^1/2, compared to 2.12±0.11 MPa m^1/2 for Cu NP-notched micro-cantilevers. Simulation results, consistent with experimental results, reveal that Cu NP-notched micro-cantilevers exhibit lower fracture resistance due to porosity and stress concentrations, while interface-notched micro-cantilevers show enhanced strength, attributed to robust bonding and reduced void distribution. Un-notched micro-cantilevers display superior load-bearing capacity, with cracks bypassing the interface and propagating through porous regions. Moreover, in un-notched micro-cantilevers, a synergistic deformation mechanism is observed, where crack propagation through the sintered Cu NPs coexists with plastic slip deformation in the Cu substrate. These findings highlight the strong interfacial bonding and effective stress transfer at the Cu substrate-sintered Cu NP interface, validating the feasibility of direct sintering using Cu NPs without additional coatings.

Sintered nano-copper (Cu) improves the thermal performance of SiC MOSFET Fan-Out Panel-Level Packaging (FOPLP), a widely adopted method for miniaturizing electronic systems and modules. This study presented, for the first time, the prototyping and characterization of a 1.2 kV SiC MOSFET FOPLP half-bridge power module using sintered nano-Cu die attachment (FOPLPCu), and compared it with a reference module using conductive Ag adhesive interconnects (FOPLP_Ag). Thermal, mechanical, and electrical co-simulations proved that FOPLPCu exhibited superior performances with lower thermal resistance, power loop parasitic inductance, and thermal deformation, achieving values of 0.14 °C/W (with double-sided cooling), 3.15 nH (@100 kHz), and 9.05e-5 m, respectively. In contrast, FOPLP_Ag showed higher values of 0.24 °C/W, 3.27 nH, and 1.04e-4 m. It is worth noting that due to the higher elastic modulus of sintered nano Cu, FOPLPCu experienced increased thermal stress. The internal structure analysis of the packaged devices, conducted using CSAM, showed that both FOPLPCu and FOPLP_Ag had well-formed interconnections, with no signs of delamination in the EMC, RDL, or interconnect layers. Thermal testing showed that FOPLPCu achieved a single-side thermal resistance of 1.95 °C/W, representing a 22% improvement compared to FOPLP_Ag's 2.5 °C/W. Electrical testing further demonstrated that FOPLPCu had lower on-state resistance compared to FOPLP_Ag, while maintaining comparable breakdown voltage, threshold voltage, and body diode forward voltage drop.