Graphdiyne (GDY)/two-dimensional materials (2DMs) heterostructures present unique opportunities for advanced optoelectronic and neuromorphic devices because of their exceptional electrical, optical, and structural properties. However, the traditional methods for construction of GDY/2DMs heterostructures usually lead to inferior interfaces, which seriously affects the charge separation and transport. Herein, an in situ approach for growing GDY nanowalls (NWs) on WSe2 is employed in this work. The as-prepared GDY NWs/WSe2 heterostructure exhibits self-powered broadband photodetection across 405–980 nm with a high responsivity of 2176 A/W and detectivity of 3.6 × 1012 Jones at 532 nm under 0.02 mW/cm2 illumination, significantly outperforming previously reported GDY-based devices. The efficient charge separation and strong photocarrier trapping in the GDY NWs/WSe2 heterostructure result in pronounced short-term and long-term synaptic plasticity. The nonlinear, wavelength-dependent reservoir state separation enables clear distinction of multiple pulse sequences, which shows great potential for logic processing. The successfully resolved red, green, and violet patterns, and one-shot color image recognition of a 5-letter image highlight transformative potential of GDY NWs/WSe2 device for future adaptive imaging and neuromorphic computing technologies.

This article compares and evaluates the single pulse short-circuit robustness of silicon carbide (SiC) MOSFETs with linear and hexagonal cell topologies under different gate voltages, bus voltages, and case temperatures. The short-circuit failure mechanisms of the linear and hexagonal cell topologies are studied. A new switching model for gate failure and thermal runaway short-circuit failure modes is proposed and analyzed. The robustness performance of the linear and hexagonal cell topologies is compared and evaluated under the same short-circuit power for the first time, fully revealing the comprehensive impact mechanism of cell topologies on the short-circuit robustness for SiC MOSFETs.

Power electronics devices, pivotal in advancing electronic system technology, are essential for energy saving, enhancing power control efficiency, reducing noise, and minimizing size and volume. The evolution of power modules is based on innovative packaging structures, technologies, and materials. This article provides a comprehensive review of inorganic nonmetallic packaging materials and technologies in power electronics packaging. It first analyzes the packaging structures and trends of power electronics. The article then discusses inorganic nonmetallic encapsulants such as cement and glass in detail. It also reviews traditional ceramic substrates and elaborates on the advantages of multilayer ceramic technologies, including low-temperature co-fired ceramics, as substrates, while looking forward to the commercialization of inorganic composite substrates such as SiCp/Al matrix composites and diamond. Subsequently, the article overviews inorganic nonmetallic fillers for thermal interface materials, emphasizing the application of two-dimensional materials such as graphene and boron nitride, and introduces inorganic nonmetallic phase change materials. Finally, it explores the application and future development trends of inorganic nonmetallic materials in embedded packaging technologies.

The mechanical strength of sintered nanoparticles (NPs) limits their application in advanced electronics packaging. In this study, we explore the anisotropy in the microstructure and mechanical properties of sintered copper (Cu) NPs by combining experimental techniques with molecular dynamics (MD) simulations. We establish a clear relationship between processing conditions, microstructural evolution, and resulting properties in pressure-assisted sintering of Cu NPs. Our findings reveal that pressure-assisted sintering induces significant anisotropy in the microstructure, as evidenced by variations in areal relative density and the orientation distribution of necks formed during sintering. Specifically, along the direction of applied pressure, the microstructure exhibits reduced variation in areal relative density and a higher prevalence of necks with favorable orientations. The resulting anisotropic mechanical properties, with significantly higher strength along the pressure direction compared to other directions, are demonstrated through micro-cantilever bending tests and tensile simulations. This anisotropy is further explained by the combined effects of strain localization (influenced by areal relative density) and the failure modes of necks (determined by their orientation relative to the loading direction). This work provides valuable insights into the analysis of sintered NPs microstructures and offers guidance for optimizing the sintering process.

Van der Waals heterojunctions (vdWHs) have garnered significant attention for their promising applications in optoelectronics, attributed to their exceptional physical attributes. In this study, we present a straightforward approach to fabricating high-performance vdWHs photodetectors. Specifically, we prepared WSO_x/WS₂ vdWH photodetectors through the ozone oxidation of a WS₂ thin films at 100 °C. To characterize the morphology and optical properties of both the WS₂ and WSO_x/WS₂ thin films, we utilized atomic force microscopy (AFM) and Raman spectroscopy. Additionally, X-ray photoelectron spectroscopy (XPS) was employed to delve into the structural evolution by scrutinizing the bonding states of W, O, and S in the WS₂ before and after the ozone oxidation process. The resultant WSO_x/WS₂ vdWH photodetectors exhibited impressive photoelectric performance at wavelengths of 475 nm and 532 nm. It demonstrated a high responsivity of 230.7 A/W, a remarkable specific detectivity of 1.794 × 10¹¹ Jones, and a swift response speed of 60 ms at 475 nm. Furthermore, first-principles calculations based on density functional theory (DFT) were conducted to validate the oxidation kinetics of monolayer WS₂, the type II energy band alignment, and the interlayer charge transfer within the WSO_x/WS₂ vdWH. This research contributes novel insights into the synthesis of two-dimensional transition metal oxides (TMOs)-transition metal dichalcogenides (TMDCs) heterostructures for photodetector applications.

This paper investigates the effects of three ageing factors (chemical, humidity, and temperature) and their interactions on the physical properties and degradation of silicone sealant used in microelectronic applications. The thermal degradation of silicone sealants was investigated by exposing samples to temperatures in the range of 150 up to 175 °C. Also, a set of samples were aged at 40 °C in a salt spray set-up with 100 % humidity in a salty atmosphere. Results showed detectable changes in the FTIR spectra of aged specimen as compared with the as-received sample. In all accelerated testing conditions, peak intensities decreased with ageing time, inferring that that the surface characteristics of the sealant is affected by ageing. Shear test results showed that with increasing the ageing time, the maximum shear stress in most cases has decreased in all ageing conditions. Also, it appears that samples with longer ageing times have experienced more elongation before failure. Results also show that salt spraying of specimens is associated with a decrease in the mechanical properties of the sealant, indicating the deleterious implications of ionic contaminations for the mechanical properties of samples.

The 1.2 kV SiC VDMOSFETs with varied JFET width (LJFET) are designed and fabricated in this study. The static and dynamic characteristics of each design are measured and compared. There is the best trade-off performance in the design of LJFET = 1.8 μm according to FOM (BV2/Ron) and FOM (Ciss/Crss). Besides, the surge capacity and evaluation for series designs are investigated under conditions of Vgs = 0 V and Vgs = −5 V. There is a best surge capacity in design of LJFET=1.2 μm, and the largest surge energy is the design of LJFET=2.0 μm. Further, the surge failure mechanisms of LJFET = 1.2 μm, 1.8 μm, and 2.0 μm under condition of Vgs = −5 V are investigated by decapsulated and FIB. Besides, the TCAD simulation was employed to theoretical analysis. The results show that the extremely high temperature was generated instantaneously under surge condition, resulting in epoxy carbonization, polysilicon melting and ILD oxide crack in failed position. Besides, the surge dissipating energy causes an instantaneous high temperature on the entire chip, resulting in aluminum remetallization. This paper would provide suggestions for device design and surge study.

The study focuses on the optical and electrical properties of Tungsten Ditelluride (WTe2), a type II Weyl semimetal, as well as the influence of its self-limiting oxide (SLO) layer that forms during natural oxidation. WTe2 exhibits promising applications in photodetection and energy harvesting due to its unique gapless linear dispersion and Berry-field-enhanced nonlinear optical effects. However, surface oxidation poses a challenge as it degrades the performance of WTe2. By employing spectroscopic ellipsometry and Raman spectroscopy, the progression of the oxide layer’s thickness and its impact on the optical constants of WTe2 were examined. The results revealed a rapid increase in oxide thickness within the first 24 h, and it reached saturation at ∼10 nm after 45 h of atmospheric exposure. Electrical properties were explored using Kelvin Probe Force Microscopy, uncovering a modification in surface potential and Fermi level following oxidation. Additionally, a SLO/WTe2 heterojunction device exhibited a wide region of positive and negative coexisting photocurrent, highlighting the potential for logical operations in ambient air. Finally, the mechanism of operation of the device is discussed. The electrical and optical properties of the pristine, partially oxidized and fully oxidized WTe2 are analyzed using density functional theory calculations. It shows that the SLO layer has a significant effect on the optical and electronic properties, which is instructive for future wavelength-modulated device optoelectronic logic operations.

With the miniaturization and high-power requirements of microelectronic devices, the current density carried by interconnects in packaging structures continually increases and reaches the threshold of electromigration (EM) failure. In this study, we investigated the microstructure evolution and void formation in aluminum (Al) interconnects during EM at three different current densities (1/3/5 MA/cm ²) and proposed a method coupling the fully coupled theory with an optimized atomic flux divergence method. The results show as follows. First, for the interconnects in integrated circuits, current density is the main factor affecting the EM lifetime of the interconnects in a certain temperature range. With the gradual increase of current density, the contribution of thermal transfer on EM cannot be ignored. The atomic concentration gradient and stress gradient can inhibit EM failure. Second, the increase of length and the decrease of width of interconnect will lead to the increase of atomic flux inside the structure, resulting in the accumulation of voids and atoms. Third, the structure is dynamically reconstructed after deleting the atoms below the failure threshold and the simulation results agree well with the experimental results. Compared with the traditional atomic flux divergence method, the improved atomic flux divergence method based on the fully coupled theory can better fit the change trend of atomic concentration after interconnect failure, and the failure time error is reduced by about 10%.

Sintered materials have been widely applied, as an alternative to soldering, for power electronics packaging. One key issue for such die-attach material is to characterize the actual porosity, which is difficult to obtain through SEM cross-section analysis. Therefore, in this work, the optimized Quartet Structure Generation Set (QSGS) algorithm was applied to sintered copper joints under various porosity levels to reconstruct 3D porous structures based on 2D SEM images. Firstly, copper joints with varying porosities were fabricated under different sintering conditions. Reconstructed 3D porous copper models were then generated through the QSGS algorithm to match experimental observations, including porosity and pore size. Finite element analysis (FEA) simulations were further conducted to explore the effects of pores on thermal and electrical performance. This work provides a method for accurately predicting the thermoelectric properties of sintered copper joints and insights for optimizing copper sintering in power electronics applications.

This Letter presents a combined analytical and experimental method to effectively decouple the radial and tangential residual stress fields induced by Berkovich nanoindentation in single-crystalline 4H-SiC using micro-Raman spectroscopy. By integrating the Raman stress characterization model with Yoffe’s expanding cavity model, precise extraction of individual residual stress components around the indentation region is realized. Through the vertical backscattering micro-Raman mapping of the E2 phonon mode, we systematically investigate the residual stress distribution near the indentation. The results highlight significant anisotropy in nanoindentation-induced stress fields, strongly dependent on the crystal orientation of 4H-SiC, predominantly featuring radial tensile stress gradients. This comprehensive theoretical–experimental approach offers a robust optical framework for residual stress characterization in 4H-SiC and provides foundational insights for extending Raman spectroscopy-based stress characterization to other crystalline materials and related device structures.

Thermal management has always played a significant role in power module design. Double-sided heat dissipation is more efficient at transferring heat than the traditional package. Although there are several thermal modeling approaches to power modules, the application of the numerical models, which are computationally fast and accurate, has rarely been investigated for double-sided heat dissipation scenarios. This paper proposes a numerical heat conduction model of a double-sided heat dissipation power module with multiple chips embedded. The model was developed by solving Laplace’s equation for the temperature distribution of steady state heat transfer using the separated variable method. The individual chip placement, two-chip distance and orientation, and four-chip placement were discussed through this modeling approach. The optimal layout was found. Then, a half-bridge topology module that consisted of two chips was investigated. To verify the accuracy of the numerical model, Finite Element Analysis (FEA) of the model was performed using the same boundary conditions. The experiments were applied on the power cycling tester to extract the junction temperature and case temperature. The numerical methods show good temperature prediction accuracy compared to both FEA and experiments.

The hexagonal cell topology of planar SiC VDMOSFETs with varied JFET width (LJFET) are designed and manufactured in this study. L JFET=1.4μ m has the best HF-FOM (R on × Cgd) and HF-FOM (R on × Qgd) by comparing the dynamic and static parameters of each design. Besides, the UIS reliability and failure mechanism for series designs are investigated by experiment and TCAD simulation. The results show that the high temperature is generated by energy dissipation during avalanche and it drives the parasitic BJT conduction, causing Ids out of control and instantaneous heat concentration in a very short time. The extremely high temperature causes internal cracking of the material and metal melting, resulting in gate-source short circuit and device damage. It would provide suggestions for device design and reliability consideration.

Resin-reinforced Ag sintering materials represent a promising solution for die-attach applications in high-power devices requiring enhanced reliability and heat dissipation. However, the presence of resin and intricate microstructure poses challenges to its thermal performance, and improvement strategies remain unclear. This work utilizes 3D FIB-SEM nanotomography to reconstruct the microstructure of this material under various process conditions. The analysis reveals that, even with an Ag volume fraction as low as 47.3%, Ag particles form a robust 3D network. Geometric tortuosity quantifies the effect of different sintering conditions on the Ag particle network in all spatial directions. Effective thermal conductivity is simulated based on realistic microstructure models. Results show a significant negative correlation between tortuosity and effective thermal conductivity. Increasing sintering temperature in Model B notably reduces tortuosity and enhances effective thermal conductivity. Sensitivity analysis underscores the dominant role of Ag volume fraction in regulating effective thermal conductivity. Finally, transient thermal impedance measurement of this material as a thin die-attach layer in actual high-power devices demonstrated its application potential. This article strives to explore the relationship between process, microstructure, and thermal properties of this material to provide a reference for further development.

Solder joint failure is one of the most common board-level failure modes in electronic components. It is crucial for a next-generation reliability assessment method to have an in-situ health monitoring system in place to evaluate the current state of degradation. This is achieved by specialized embedded sensors and processing the data on the edge. This study focuses on monitoring the mechanical degradation of package-to-PCB solder interconnects of a WLCSP using a high-resolution piezoresistive sensor. First, a measurement workflow was set up to optimize and significantly improve the sensor readout time. Then, utilizing a design of experiments, the test specimens were subjected to certain combinations of mechanical and thermal loads in a four-point bending setup. Temperature-coupled mechanical loading showed a greater impact on the resulting stress pattern compared to that of a superposition of the corresponding individual purely thermal and mechanical load configurations. Finally, the specimens were tested under a purely mechanical load until failure, and a correlation between the recorded stress pattern and the initiation and propagation of a crack was established.

The primary challenges posed by oral mucosal diseases are their high incidence and the difficulty in managing symptoms. Inspired by the ability of bioelectricity to activate cells, accelerate metabolism, and enhance immunity, a conductive polyacrylamide/sodium alginate crosslinked hydrogel composite containing reduced graphene oxide (PAA-SA@rGO) is developed. This composite possesses antibacterial, anti-inflammatory, and antioxidant properties, serving as a bridge to turn the “short circuit” of the injured site into a “completed circuit,” thereby prompting fibroblasts in proximity to the wound site to secrete growth factors and expedite tissue regeneration. Simultaneously, the PAA-SA@rGO hydrogel effectively seals wounds to form a barrier, exhibits antibacterial and anti-inflammatory properties, and prevents foreign bacterial invasion. As the electric field of the wound is rebuilt and repaired by the PAA-SA@rGO hydrogel, a 5 × 5 mm² wound in the full-thickness buccal mucosa of rats can be expeditiously mended within mere 7 days. The theoretical calculations indicate that the PAA-SA@rGO hydrogel can aggregate and express SOX2, PITX1, and PITX2 at the wound site, which has a promoting effect on rapid wound healing. Importantly, this PAA-SA@rGO hydrogel has a fast curative effect and only needs to be applied for the first three days, which significantly improves patient satisfaction during treatment.

Integrated circuits based on wide bandgap semiconductors are considered an attractive option for meeting the demand for high-temperature electronics. Here, we report an analog-to-digital converter fabricated in a silicon carbide complementary metal-oxide-semiconductor technology now available through Europractice. The MOSFET component in this technology was measured up to 500 °C, and the key parameters, such as threshold voltage, field-effect mobility, and channel-length modulation parameters, were extracted. A 4-bit flash data converter, consisting of 266 transistors, is implemented with this technology and demonstrates correct operation up to 400 °C. Finally, the gate oxide quality is investigated by time-dependent dielectric breakdown measurements at 500 °C. A field-acceleration factor of 4.4 dec/(MV/cm) is obtained by applying the E model.

The authors regret that in the above article the Fig. 3 contains an error of cross-section image of group C at 48 h on Page 4. Fig. 3 should read: This correction does not influence the method, results and conclusions of the original article. The authors would like to apologise for any inconvenience caused.

With the advancement of power electronics, aluminum-clad copper thick bonding wires have garnered attentions due to superior electrical and thermal properties, making them well-suited for high-temperature and high-current applications. However, the impact remains unveiled of whether the growth of intermetallic compounds (IMCs) at the bonding interface presents critical challenges to the reliability of wedge wire bonds. Therefore, it is necessary to investigate the evolution behavior of Cu/Al IMCs in Al-clad copper wires. In this study, Scanning Electron Microscopy (SEM) and Transmission Electron Microscopy (TEM) were firstly employed to characterize the phase composition and growth behavior of Cu/Al intermetallic compounds (IMCs) at two distinct interfaces—the bonding interface and the core-shell interface—under various annealing conditions during high-temperature storage (HTS) tests, revealing a parabolic relationship between aging time and IMCs thickness. Subsequently, shear and pull tests of Al-clad copper bond wires were conducted to evaluate the bonding strength under different aging conditions, clarifying the correlation between various failure modes of the bonds and the evolution of IMCs at the bi-interfaces of this novel composite across different aging stages. Additionally, molecular dynamics (MD) simulations were employed to explore the diffusion behavior of Cu and Al atoms. It revealed that polycrystalline structures enhanced the mutual diffusion at the interface, with copper serving as the predominant element in the interdiffusion process. In conclusion, this study integrates experimental and numerical approaches to elucidate the growth mechanisms of Cu/Al intermetallic compounds and their effects on reliability, providing valuable guidance for optimizing the performance of composite bonding wires in high-temperature power device applications.

Electromigration (EM) is a crucial failure mode in Aluminum (Al) interconnection wires those are widely used in high density semiconductor packaging. This study systematically investigated the influence of EM on the mechanical properties of Al interconnects via nanoindentation experiments and molecular dynamics (MD) simulations. The results are list as follows. (1) The indentation depth gradually increases with the increase in indentation load, resulting in a gradual increase and stabilization of the Young’s modulus and hardness of the structure. Within a specific range, the influence of the loading rate on the indentation depth and mechanical properties is relatively small. (2) The region where Young’s modulus of the interconnect decreases correlates with the location where EM-induced voids initiate. EM-induced voids have a direct impact on the material’s mechanical properties, particularly the decrease in Young’s modulus. (3) These EM-induced voids affect the nucleation and formation of dislocations. With the increase in void concentration and indentation depth, The generation and slip of dislocations increase as the void concentration and indentation depth increase, leading to a decrease in the material’s mechanical properties over time. This comprehensive findings expand the knowledge on mechanical behavior degradation of Al interconnects when EM failure occurs, providing a scientific basis for designing and optimizing high density semiconductor packaging.