The heat produced within the device in its package depends on the power supplied to each IP block. The improper placement of an IP block with high power consumption can become a reliability risk for IC packages, as it can significantly affect the reliability of solder balls due to thermal, mechanical, and electrical factors. It also mitigates the effect of thermal cycling, because it depends upon heat management within the package. Improper IP block placement can block heat flow paths, which results in poor thermal dissipation and higher temperature which can create a higher strain on the solder balls affecting their lifetime. Therefore, it is crucial to understand the interplay between the correct placement of IP blocks and solder balls to enhance solder ball reliability. COMSOL-based simulation study will be done on a WLCSP (Wafer Level Chip Scale Package) mounted on a PCB board on which solder balls are connected to copper layers on the die and PCB sides. Variations in the placement of the IP blocks. Thermal cycling and the variations in the placement of the IP block within the package will be taken as a loading condition. Therefore, this influences the susceptibility of device failure due to solder ball fatigue. Based on board-level passive cycling, the solder balls which are located under the IP blocks are the most likely ones affected by this stress. The results will be analyzed to optimize the layout of the IP blocks, concerning accumulated plastic strain on the solder balls at different locations of the IP block placement. It can help to understand the influence of the position of the IP block, reduce stress concentration, and minimize thermal cycling effects, which leads to an increase in the reliability of the solders joint and IC package itself.

Silicon-Carbide (SiC) MOSFETs are widely used in high-power and high-efficiency applications such as electric vehicles and power supplies. However, long-term reliability remains a critical concern, particularly under extreme operating conditions. This work aims to explain the health monitoring of SiC metal oxide-semiconductor field effect transistors (MOSFETs) through precise junction temperature (T_j) profiling based on performed measurements. The study focuses on the temperature-dependent behavior of the on-resistance (RDS(on)), a key parameter that varies with the aging, degradation, and temperature of the device. By systematically measuring R_DS(on) at different temperatures and at various stages of the operating life of the device, we can establish a predictive model to assess the health of SiC MOSFETs. The importance of pulse duration of the drain current is stressed to avoid the self-heating effect with some device physics insights. The proposed methodology enables better understanding of the SiC MOSFET performance for future real-time condition monitoring, facilitating early failure detection and lifetime estimation. This approach provides valuable information for improving reliability and optimizing maintenance strategies in power electronics systems. Experimental results validate the effectiveness of the proposed method and give direction for future research opportunities.

This Letter presents a combined analytical and experimental method to effectively decouple the radial and tangential residual stress fields induced by Berkovich nanoindentation in single-crystalline 4H-SiC using micro-Raman spectroscopy. By integrating the Raman stress characterization model with Yoffe’s expanding cavity model, precise extraction of individual residual stress components around the indentation region is realized. Through the vertical backscattering micro-Raman mapping of the E2 phonon mode, we systematically investigate the residual stress distribution near the indentation. The results highlight significant anisotropy in nanoindentation-induced stress fields, strongly dependent on the crystal orientation of 4H-SiC, predominantly featuring radial tensile stress gradients. This comprehensive theoretical–experimental approach offers a robust optical framework for residual stress characterization in 4H-SiC and provides foundational insights for extending Raman spectroscopy-based stress characterization to other crystalline materials and related device structures.

With the miniaturization and high-power requirements of microelectronic devices, the current density carried by interconnects in packaging structures continually increases and reaches the threshold of electromigration (EM) failure. In this study, we investigated the microstructure evolution and void formation in aluminum (Al) interconnects during EM at three different current densities (1/3/5 MA/cm ²) and proposed a method coupling the fully coupled theory with an optimized atomic flux divergence method. The results show as follows. First, for the interconnects in integrated circuits, current density is the main factor affecting the EM lifetime of the interconnects in a certain temperature range. With the gradual increase of current density, the contribution of thermal transfer on EM cannot be ignored. The atomic concentration gradient and stress gradient can inhibit EM failure. Second, the increase of length and the decrease of width of interconnect will lead to the increase of atomic flux inside the structure, resulting in the accumulation of voids and atoms. Third, the structure is dynamically reconstructed after deleting the atoms below the failure threshold and the simulation results agree well with the experimental results. Compared with the traditional atomic flux divergence method, the improved atomic flux divergence method based on the fully coupled theory can better fit the change trend of atomic concentration after interconnect failure, and the failure time error is reduced by about 10%.

The 1.2 kV SiC VDMOSFETs with varied JFET width (LJFET) are designed and fabricated in this study. The static and dynamic characteristics of each design are measured and compared. There is the best trade-off performance in the design of LJFET = 1.8 μm according to FOM (BV2/Ron) and FOM (Ciss/Crss). Besides, the surge capacity and evaluation for series designs are investigated under conditions of Vgs = 0 V and Vgs = −5 V. There is a best surge capacity in design of LJFET=1.2 μm, and the largest surge energy is the design of LJFET=2.0 μm. Further, the surge failure mechanisms of LJFET = 1.2 μm, 1.8 μm, and 2.0 μm under condition of Vgs = −5 V are investigated by decapsulated and FIB. Besides, the TCAD simulation was employed to theoretical analysis. The results show that the extremely high temperature was generated instantaneously under surge condition, resulting in epoxy carbonization, polysilicon melting and ILD oxide crack in failed position. Besides, the surge dissipating energy causes an instantaneous high temperature on the entire chip, resulting in aluminum remetallization. This paper would provide suggestions for device design and surge study.

Sintered materials have been widely applied, as an alternative to soldering, for power electronics packaging. One key issue for such die-attach material is to characterize the actual porosity, which is difficult to obtain through SEM cross-section analysis. Therefore, in this work, the optimized Quartet Structure Generation Set (QSGS) algorithm was applied to sintered copper joints under various porosity levels to reconstruct 3D porous structures based on 2D SEM images. Firstly, copper joints with varying porosities were fabricated under different sintering conditions. Reconstructed 3D porous copper models were then generated through the QSGS algorithm to match experimental observations, including porosity and pore size. Finite element analysis (FEA) simulations were further conducted to explore the effects of pores on thermal and electrical performance. This work provides a method for accurately predicting the thermoelectric properties of sintered copper joints and insights for optimizing copper sintering in power electronics applications.

Graphdiyne (GDY)/two-dimensional materials (2DMs) heterostructures present unique opportunities for advanced optoelectronic and neuromorphic devices because of their exceptional electrical, optical, and structural properties. However, the traditional methods for construction of GDY/2DMs heterostructures usually lead to inferior interfaces, which seriously affects the charge separation and transport. Herein, an in situ approach for growing GDY nanowalls (NWs) on WSe2 is employed in this work. The as-prepared GDY NWs/WSe2 heterostructure exhibits self-powered broadband photodetection across 405–980 nm with a high responsivity of 2176 A/W and detectivity of 3.6 × 1012 Jones at 532 nm under 0.02 mW/cm2 illumination, significantly outperforming previously reported GDY-based devices. The efficient charge separation and strong photocarrier trapping in the GDY NWs/WSe2 heterostructure result in pronounced short-term and long-term synaptic plasticity. The nonlinear, wavelength-dependent reservoir state separation enables clear distinction of multiple pulse sequences, which shows great potential for logic processing. The successfully resolved red, green, and violet patterns, and one-shot color image recognition of a 5-letter image highlight transformative potential of GDY NWs/WSe2 device for future adaptive imaging and neuromorphic computing technologies.

This paper investigates the effects of three ageing factors (chemical, humidity, and temperature) and their interactions on the physical properties and degradation of silicone sealant used in microelectronic applications. The thermal degradation of silicone sealants was investigated by exposing samples to temperatures in the range of 150 up to 175 °C. Also, a set of samples were aged at 40 °C in a salt spray set-up with 100 % humidity in a salty atmosphere. Results showed detectable changes in the FTIR spectra of aged specimen as compared with the as-received sample. In all accelerated testing conditions, peak intensities decreased with ageing time, inferring that that the surface characteristics of the sealant is affected by ageing. Shear test results showed that with increasing the ageing time, the maximum shear stress in most cases has decreased in all ageing conditions. Also, it appears that samples with longer ageing times have experienced more elongation before failure. Results also show that salt spraying of specimens is associated with a decrease in the mechanical properties of the sealant, indicating the deleterious implications of ionic contaminations for the mechanical properties of samples.

The mechanical strength of sintered nanoparticles (NPs) limits their application in advanced electronics packaging. In this study, we explore the anisotropy in the microstructure and mechanical properties of sintered copper (Cu) NPs by combining experimental techniques with molecular dynamics (MD) simulations. We establish a clear relationship between processing conditions, microstructural evolution, and resulting properties in pressure-assisted sintering of Cu NPs. Our findings reveal that pressure-assisted sintering induces significant anisotropy in the microstructure, as evidenced by variations in areal relative density and the orientation distribution of necks formed during sintering. Specifically, along the direction of applied pressure, the microstructure exhibits reduced variation in areal relative density and a higher prevalence of necks with favorable orientations. The resulting anisotropic mechanical properties, with significantly higher strength along the pressure direction compared to other directions, are demonstrated through micro-cantilever bending tests and tensile simulations. This anisotropy is further explained by the combined effects of strain localization (influenced by areal relative density) and the failure modes of necks (determined by their orientation relative to the loading direction). This work provides valuable insights into the analysis of sintered NPs microstructures and offers guidance for optimizing the sintering process.

The study focuses on the optical and electrical properties of Tungsten Ditelluride (WTe2), a type II Weyl semimetal, as well as the influence of its self-limiting oxide (SLO) layer that forms during natural oxidation. WTe2 exhibits promising applications in photodetection and energy harvesting due to its unique gapless linear dispersion and Berry-field-enhanced nonlinear optical effects. However, surface oxidation poses a challenge as it degrades the performance of WTe2. By employing spectroscopic ellipsometry and Raman spectroscopy, the progression of the oxide layer’s thickness and its impact on the optical constants of WTe2 were examined. The results revealed a rapid increase in oxide thickness within the first 24 h, and it reached saturation at ∼10 nm after 45 h of atmospheric exposure. Electrical properties were explored using Kelvin Probe Force Microscopy, uncovering a modification in surface potential and Fermi level following oxidation. Additionally, a SLO/WTe2 heterojunction device exhibited a wide region of positive and negative coexisting photocurrent, highlighting the potential for logical operations in ambient air. Finally, the mechanism of operation of the device is discussed. The electrical and optical properties of the pristine, partially oxidized and fully oxidized WTe2 are analyzed using density functional theory calculations. It shows that the SLO layer has a significant effect on the optical and electronic properties, which is instructive for future wavelength-modulated device optoelectronic logic operations.

This article compares and evaluates the single pulse short-circuit robustness of silicon carbide (SiC) MOSFETs with linear and hexagonal cell topologies under different gate voltages, bus voltages, and case temperatures. The short-circuit failure mechanisms of the linear and hexagonal cell topologies are studied. A new switching model for gate failure and thermal runaway short-circuit failure modes is proposed and analyzed. The robustness performance of the linear and hexagonal cell topologies is compared and evaluated under the same short-circuit power for the first time, fully revealing the comprehensive impact mechanism of cell topologies on the short-circuit robustness for SiC MOSFETs.

Van der Waals heterojunctions (vdWHs) have garnered significant attention for their promising applications in optoelectronics, attributed to their exceptional physical attributes. In this study, we present a straightforward approach to fabricating high-performance vdWHs photodetectors. Specifically, we prepared WSO_x/WS₂ vdWH photodetectors through the ozone oxidation of a WS₂ thin films at 100 °C. To characterize the morphology and optical properties of both the WS₂ and WSO_x/WS₂ thin films, we utilized atomic force microscopy (AFM) and Raman spectroscopy. Additionally, X-ray photoelectron spectroscopy (XPS) was employed to delve into the structural evolution by scrutinizing the bonding states of W, O, and S in the WS₂ before and after the ozone oxidation process. The resultant WSO_x/WS₂ vdWH photodetectors exhibited impressive photoelectric performance at wavelengths of 475 nm and 532 nm. It demonstrated a high responsivity of 230.7 A/W, a remarkable specific detectivity of 1.794 × 10¹¹ Jones, and a swift response speed of 60 ms at 475 nm. Furthermore, first-principles calculations based on density functional theory (DFT) were conducted to validate the oxidation kinetics of monolayer WS₂, the type II energy band alignment, and the interlayer charge transfer within the WSO_x/WS₂ vdWH. This research contributes novel insights into the synthesis of two-dimensional transition metal oxides (TMOs)-transition metal dichalcogenides (TMDCs) heterostructures for photodetector applications.

In this study, we introduced a hybrid Potts-phase field model to simulate the co-evolution of grain growth and pores migration in sintered silver layers. The Potts model is good at capture the grain growth dynamics, while the phase field model describes the evolution of the porous network. These models are coupled via a hybrid free energy function to achieve a realistic representation of the microstructure evolution. This study further extends the hybrid model by incorporating (a) a flexible exchange interaction matrix to model the crystal anisotropy in grain growth, (b) Glauber or Kawasaki dynamics to describe different diffusion mechanisms, and (c) the effect of pinning sites, representing impurity-driven grain boundary stabilization. The computational framework is implemented using Taichi Lang, which allows for efficient parallel simulations. Results show that the model effectively captures the long-term evolution of the sintered silver microstructure in good agreement with experimental observations. This hybrid model is a powerful tool to predict microstructural reliability of sintered silver die attach layers, supporting material design and process optimization for high-power electronic applications.

This study presents a novel approach for localized silver (Ag) nanoparticles (NPs) sintering using microheater arrays embedded within the Si substrate. By applying controlled pulse currents, these microheaters generate targeted heat pulses, enabling rapid and localized sintering while maintaining the surrounding device components at room temperature. This localized heating minimizes thermal stress caused by thermal expansion mismatches, as sintering completes within milliseconds. Compared to conventional sintering techniques, this method improves process efficiency, reduces power consumption, and provides precise spatial control over the sintered regions. The proposed approach offers a promising alternative for microelectronics packaging and integration, particularly in applications requiring precise thermal management.

Power electronics devices, pivotal in advancing electronic system technology, are essential for energy saving, enhancing power control efficiency, reducing noise, and minimizing size and volume. The evolution of power modules is based on innovative packaging structures, technologies, and materials. This article provides a comprehensive review of inorganic nonmetallic packaging materials and technologies in power electronics packaging. It first analyzes the packaging structures and trends of power electronics. The article then discusses inorganic nonmetallic encapsulants such as cement and glass in detail. It also reviews traditional ceramic substrates and elaborates on the advantages of multilayer ceramic technologies, including low-temperature co-fired ceramics, as substrates, while looking forward to the commercialization of inorganic composite substrates such as SiCp/Al matrix composites and diamond. Subsequently, the article overviews inorganic nonmetallic fillers for thermal interface materials, emphasizing the application of two-dimensional materials such as graphene and boron nitride, and introduces inorganic nonmetallic phase change materials. Finally, it explores the application and future development trends of inorganic nonmetallic materials in embedded packaging technologies.

Corrosion protection is one of the most important issues when copper is applied in power electronics packaging as bonding wire, die attachment, interconnection, and DBC substrate. Covering a layer of corrosion-resistant encapsulation material is a worthy consideration to protect copper. In this paper, the corrosion-resistant effects of two organic encapsulation materials, polydimethylsiloxane (PDMS) and hexamethyldisiloxane (HMDSO), on the copper surface were performed by molecular dynamics simulations. Firstly, the Cu-coating bilayer models were constructed, and the binding performances of the encapsulation material/copper interface were evaluated through calculating their interaction energy, proving that the organic coatings can form interconnection on copper surface. Then, the diffusion processes of corrosive gas molecules (H₂S, H₂O and O₂) into the copper layer under different coating conditions were simulated, and both coatings exhibited good corrosion protection performances. The above results indicate that both PDMS and HMDSO have promising potential for copper corrosion protection in power electronics packaging. This may provide some guidance for corrosion protection of copper material used in power electronics packaging.

As the dimensions of interconnects in integrated circuits continue to shrink, an urgent need arises to understand the physical mechanism associated with electromigration. Using x-ray nanodiffraction, we analyzed the stresses in Blech-structured pure Cu lines subjected to different electromigration conditions. The results suggest that the measured residual stresses in the early stages of electromigration are related to relaxation of stresses caused by thermal expansion mismatch, while a developing current-induced stress leads to reductions in the residual stress after longer test times. These findings not only validate the feasibility of measuring stress in copper lines using nanodiffraction but also highlight the need for a further understanding, particularly through in situ electromigration experiments with x-ray nanodiffraction analysis.

Integrated circuits based on wide bandgap semiconductors are considered an attractive option for meeting the demand for high-temperature electronics. Here, we report an analog-to-digital converter fabricated in a silicon carbide complementary metal-oxide-semiconductor technology now available through Europractice. The MOSFET component in this technology was measured up to 500 °C, and the key parameters, such as threshold voltage, field-effect mobility, and channel-length modulation parameters, were extracted. A 4-bit flash data converter, consisting of 266 transistors, is implemented with this technology and demonstrates correct operation up to 400 °C. Finally, the gate oxide quality is investigated by time-dependent dielectric breakdown measurements at 500 °C. A field-acceleration factor of 4.4 dec/(MV/cm) is obtained by applying the E model.

Board level reliability can be of high interest for automotive electronic components when exposed to vibration-prone environments. However, the absence of an industry standard for board level vibration testing poses several challenges in establishing a well-characterized test setup. One of the challenges is that automotive applications can induce abnormal stresses on components that can lead to early failures in the field. Such loading conditions are not always covered in the current board level vibration test methods. This paper aims to correlate the stresses from automotive modules to board levels by measuring the printed circuit board (PCB) vibration spectrum. Firstly, the study compares and assesses several module board level vibration measurement units, such as LASER Doppler Vibrometer (LDV), strain gauges, and accelerometers. Experiments and simulations show that LDV enables good correlation with Micro-electro Mechanical Systems (MEMS) accelerometers. Secondly, the module-board interaction unveils insights into several module design features that impact the PCB vibration response and solder joint interconnect reliability. These findings underscore the necessity for the user to correctly validate the reliability of packages beyond board level testing, i.e., at the module level. This reliability test approach enables the translation of reliability test results from the lab to the field life of components once built in the final application equipment.

Synchronized rectifiers offer promising solutions for piezoelectric energy harvesting; however, achieving the promised energy extraction performance necessitates using either a bulky inductor or multiple large capacitors, which cannot be on-chip integrated and increase the system form factor. This article introduces a fully integrated sequenced synchronized switch harvesting on capacitors (3SHC) rectifier. The input piezoelectric transducer (PT) uses microelectromechanical system technology. The cantilever is equally split into multiple strongly coupled subcantilevers, with each cantilever treated as an individual PT connected to the proposed rectifier. The 3SHC rectifier cyclically operates multiple times to synchronously flip the voltage of each cantilever sequentially. With the proposed design, all the flying capacitors only need to match the capacitance of each subcantilever; hence, they can be fully integrated on-chip. The design is fabricated using standard 0.18 μ m CMOS technology. Measurement results show that the proposed 3SHC rectifier attains an 80% voltage flip efficiency and achieves a 730% power enhancement compared to a full-bridge rectifier.