Solder joint reliability related to failures due to thermomechanical loading is a critically important yet physically complex engineering problem. As a result, simulated behavior is oftentimes computationally expensive. In an increasingly data-driven world, it is popular to use efficient data-driven design schemes. Among the family of efficient optimization methods, Bayesian optimization with Gaussian process regression is a key representative. The authors argue that additional computational savings can be obtained from exploiting thorough surrogate modeling and selecting a design candidate based on multiple acquisition functions. This is feasible due to the relatively low computational cost, compared to the expensive simulation objective. This paper presents a novel heuristic framework for performing Bayesian optimization with adaptive hyperparameters across multiple optimization iterations. A comparative study shows the ability of adaptive Bayesian optimization to save on expensive objective evaluations with respect to the worst-performing regular Bayesian optimization scheme. As an engineering use case, the solder joint reliability problem is tackled by minimizing the accumulated non-linear creep strain under a cyclic thermal load. Results show that adaptive Bayesian optimization can at least match the performance of regular Bayesian optimization in terms of raw objective performance, but achieves this with half of the computational expense budget. This practical result underlines the methodological potential of the novel adaptive Bayesian data-driven methodology to achieve more efficient results and significantly cut optimization-related expenses. Lastly, to promote the reproducibility of the results, the data-driven implementations are made available on an open-source basis.

Residual stress and thermally induced warpage are critical reliability concerns in power electronic packaging, particularly when employing sintered copper nanoparticle (Cu NP) interconnects. While these interconnects provide high thermal and electrical performance, they also introduce significant interfacial stresses during bonding that alter mechanical behavior during service. This study develops an integrated confocal Raman–analytical modeling framework to directly quantify and mechanistically interpret these stresses in a representative SiC/Sintered Cu NPs/Active Metal Brazing ceramic substrate (AMB) stack. Raman spectroscopy reveals a compressive interfacial stress field peaking at −334 MPa near the chip center with localized hotspots linked to microporosity. Complementary in-situ Moiré interferometry tracked warpage evolution during thermal cycle (30–310°C). Coupling this stress measurement with a three-dimensional thermoelastic model, and explicitly assigning the bonding temperature as the stress-free reference, enables accurate reproduction of the temperature-dependent warpage trajectory. The model predictions align with experimental interferometry within < 5% deviation. These results demonstrate that incorporating residual stress is essential to realistically capture thermo-mechanical evolution. The proposed Raman–model paradigm advances beyond prior purely numerical or purely experimental efforts by bridging quantitative stress mapping with predictive warpage modeling. This methodology provides essential insights for thermal-induced residual stress and warpage managements in high-temperature power electronics packaging, providing a stress-informed foundation for reliability assessment and design optimization.

This study investigates the interface strength and fracture behavior of sintered copper (Cu) nanoparticles (NPs) for all-Cu integration in advanced microelectronics packaging. Micro-cantilever bending tests on three configurations (Cu NP-notched, interface-notched and un-notched micro-cantilevers) were analyzed using scanning electron microscopy (SEM), transmission electron microscopy (TEM), transmission Kikuchi diffraction (TKD) and cohesive zone model (CZM). The interface-notched micro-cantilevers demonstrate superior fracture resistance, with a stress intensity factor (K_Q) of 2.88±0.10 MPa m^1/2, compared to 2.12±0.11 MPa m^1/2 for Cu NP-notched micro-cantilevers. Simulation results, consistent with experimental results, reveal that Cu NP-notched micro-cantilevers exhibit lower fracture resistance due to porosity and stress concentrations, while interface-notched micro-cantilevers show enhanced strength, attributed to robust bonding and reduced void distribution. Un-notched micro-cantilevers display superior load-bearing capacity, with cracks bypassing the interface and propagating through porous regions. Moreover, in un-notched micro-cantilevers, a synergistic deformation mechanism is observed, where crack propagation through the sintered Cu NPs coexists with plastic slip deformation in the Cu substrate. These findings highlight the strong interfacial bonding and effective stress transfer at the Cu substrate-sintered Cu NP interface, validating the feasibility of direct sintering using Cu NPs without additional coatings.

Fan-Out Panel Level Package has become a trend in Silicon Carbide MOSFET packaging due to its superior electrothermal performance and cost-effectiveness. However, the increased size of multi-chip embedded FOPLP packaging introduces greater challenges in sample preparation and thermal-mechanical stresses. In this paper, a large-sized (20mm*20mm*0.78mm) FOPLP with 4 SiC MOSFETs embedded is investigated. A three-dimensional thermal-mechanical numerical model is derived based on heat conduction and elasticity theories. It utilized analytical solution of Fourier temperature conduction and finite difference results for thermoelastic models to describe the temperature and deformation distribution during the FOPLP operation. It also reveals the heat coupling issue of multiple chips. Compared with the finite element simulation, the proposed method shows less than 2.5 % error in temperature and 2.3 % error in deformation. The computational speed is one-tenth that of the finite element method, while the memory usage is reduced to one-fifth. To mitigate the influence of chip thermal coupling on temperature and warpage, an optimized layout was employed to achieve temperature uniformity improvement. Finally, FOPLPs with the two layouts were fabricated. The warpage was monitored using a digital image correlation platform. To achieve the same temperature, the current required for the optimized layout was increased by 9 %. The warpage of the optimized layout at 60 °C was reduced by 13.5 %, and at 100 °C it was reduced by 14.7 %, validating the accuracy of the model and the significance of thermal-decoupling.

4H-SiC is widely employed in power electronic devices operating under high frequencies, voltages, and temperatures due to its exceptional physical properties. However, its inherent high hardness and elastic modulus induce inevitable residual stress during device fabrication. Raman spectroscopy, which leverages lattice dynamics, offers an effective, non-destructive, rapid, and contactless method for measuring these stresses. Nevertheless, its accuracy critically depends on precisely determining the Raman phonon deformation potential constant. This work investigates mechanically induced Raman shifts in 4H-SiC via first-principles calculations and in-situ Raman spectroscopy under hydrostatic and non-hydrostatic stress conditions. The E2(TO) and A1(LO) phonon modes exhibit sensitivity to hydrostatic stress, whereas A1(LO) remains largely unaffected under shear, reflecting directional vibrational differences. Theoretical predictions and experimental measurements agree well within 16% error, highlighting the effectiveness of Raman-based stress detection for 4H-SiC. This integrated theoretical–experimental approach provides a robust framework for stress and strain analysis, facilitating the design and fabrication of next-generation 4H-SiC electronic devices.

This paper investigates the effects of three ageing factors (chemical, humidity, and temperature) and their interactions on the physical properties and degradation of silicone sealant used in microelectronic applications. The thermal degradation of silicone sealants was investigated by exposing samples to temperatures in the range of 150 up to 175 °C. Also, a set of samples were aged at 40 °C in a salt spray set-up with 100 % humidity in a salty atmosphere. Results showed detectable changes in the FTIR spectra of aged specimen as compared with the as-received sample. In all accelerated testing conditions, peak intensities decreased with ageing time, inferring that that the surface characteristics of the sealant is affected by ageing. Shear test results showed that with increasing the ageing time, the maximum shear stress in most cases has decreased in all ageing conditions. Also, it appears that samples with longer ageing times have experienced more elongation before failure. Results also show that salt spraying of specimens is associated with a decrease in the mechanical properties of the sealant, indicating the deleterious implications of ionic contaminations for the mechanical properties of samples.

Sintered nano-copper (Cu) improves the thermal performance of SiC MOSFET Fan-Out Panel-Level Packaging (FOPLP), a widely adopted method for miniaturizing electronic systems and modules. This study presented, for the first time, the prototyping and characterization of a 1.2 kV SiC MOSFET FOPLP half-bridge power module using sintered nano-Cu die attachment (FOPLPCu), and compared it with a reference module using conductive Ag adhesive interconnects (FOPLP_Ag). Thermal, mechanical, and electrical co-simulations proved that FOPLPCu exhibited superior performances with lower thermal resistance, power loop parasitic inductance, and thermal deformation, achieving values of 0.14 °C/W (with double-sided cooling), 3.15 nH (@100 kHz), and 9.05e-5 m, respectively. In contrast, FOPLP_Ag showed higher values of 0.24 °C/W, 3.27 nH, and 1.04e-4 m. It is worth noting that due to the higher elastic modulus of sintered nano Cu, FOPLPCu experienced increased thermal stress. The internal structure analysis of the packaged devices, conducted using CSAM, showed that both FOPLPCu and FOPLP_Ag had well-formed interconnections, with no signs of delamination in the EMC, RDL, or interconnect layers. Thermal testing showed that FOPLPCu achieved a single-side thermal resistance of 1.95 °C/W, representing a 22% improvement compared to FOPLP_Ag's 2.5 °C/W. Electrical testing further demonstrated that FOPLPCu had lower on-state resistance compared to FOPLP_Ag, while maintaining comparable breakdown voltage, threshold voltage, and body diode forward voltage drop.

The three-step wet etching (TSWE) method has been proven to be a promising technique for fabricating silicon nanopores. Despite its potential, one of the bottlenecks of this method is the precise control of the silicon etching and etch-stop, which results in obtaining a well-defined nanopore size. Herein, we present a novel strategy leveraging electrochemical passivation to achieve accurate control over the silicon etching process. By dynamically controlling the oxide layer growth, rapid and reliable etch-stop was achieved in under 4 s, enabling the controllable fabrication of sub-10 nm silicon nanopores. The thickness of the oxide layer was precisely modulated by adjusting the passivation potential, achieving nanopore size shrinkage with a precision better than 2 nm, which can be further enhanced with more refined potential control. This scalable method significantly enhances the TSWE process, offering an efficient approach for producing small-size silicon nanopores with high precision. Importantly, the precise etching control facilitated by electrochemical passivation holds promise for the cost-effective production of high-density, air-insulated monolithic integrated circuits. (Figure presented.)

In harsh offshore environments, large-area sintered nano-copper (Cu) interconnections, which serve as die attachment material or thermal interface material (TIM), are prone to degradation from hydrogen sulfide (H2S) corrosion. This study introduced a film-forming technique based on atmospheric pressure plasma jet (APPJ) to improve the corrosion resistance of large-area sintered nanoCu joint. The corrosion protection mechanism against H2S-containing atmospheric corrosion was investigated using both experimental methods and density functional theory (DFT) simulations. The key findings were as follows: (1) The deposition film, primarily composed of a Si-O3 network, effectively protected sintered Cu plate from corrosion by H2S gas, and maintaining the mechanical performance of sintered Cu joint after 384 h of H2S testing. (2) The dissociation products of the APPJ-treated precursor hexamethyldisiloxane (HMDSO), −OSiCH3 and −OSi(CH3)3, formed stable chemical bonds on the sintered nanoCu surface, resulting in the formation of −OSiCH3(O-CH3)2 fragments. (3) The −OSiCH3(O-CH3)2 fragments were unreactive toward to corrosion agents such as H2S, O2, and H2O, and also serving as a barrier to block their access to the sintered nanoCu surface. This study provided a comprehensive understanding of the corrosion protection mechanism of sintered nanoCu using APPJ-deposited films, offering valuable insights for improving the reliability of power electronics.

The use of microRNAs as clinical cancer biomarkers is hindered by the absence of accurate, sensitive and rapid assays for their detection in biofluids. Here we report a biosensing approach, SpLig-HEMT, that combines an RNA splint-ligation reaction with an AlGaN/GaN high-electron-mobility transistor biosensor for ultrasensitive miRNA detection. In this system, HEMT functions as a highly effective voltage amplifier to enhance detection sensitivity, while the splint-ligation reaction ensures precise discrimination of single-nucleotide mutations. By detecting miRNA-21, the SpLig-HEMT biosensor achieves an exceptional limit of detection of 10⁻¹⁸ M within 30 min, with a dynamic range from 10⁻¹⁸ M to 10⁻¹³ M. No detectable response is observed for one-mismatch miR-21. Furthermore, the SpLig-HEMT biosensor enables direct analysis of blood serum samples, effectively distinguishing between healthy individuals and patients with ovarian cancer. This study addresses critical challenges in miRNA detection and presents a promising tool for cancer diagnosis and prognosis.

The heat produced within the device in its package depends on the power supplied to each IP block. The improper placement of an IP block with high power consumption can become a reliability risk for IC packages, as it can significantly affect the reliability of solder balls due to thermal, mechanical, and electrical factors. It also mitigates the effect of thermal cycling, because it depends upon heat management within the package. Improper IP block placement can block heat flow paths, which results in poor thermal dissipation and higher temperature which can create a higher strain on the solder balls affecting their lifetime. Therefore, it is crucial to understand the interplay between the correct placement of IP blocks and solder balls to enhance solder ball reliability. COMSOL-based simulation study will be done on a WLCSP (Wafer Level Chip Scale Package) mounted on a PCB board on which solder balls are connected to copper layers on the die and PCB sides. Variations in the placement of the IP blocks. Thermal cycling and the variations in the placement of the IP block within the package will be taken as a loading condition. Therefore, this influences the susceptibility of device failure due to solder ball fatigue. Based on board-level passive cycling, the solder balls which are located under the IP blocks are the most likely ones affected by this stress. The results will be analyzed to optimize the layout of the IP blocks, concerning accumulated plastic strain on the solder balls at different locations of the IP block placement. It can help to understand the influence of the position of the IP block, reduce stress concentration, and minimize thermal cycling effects, which leads to an increase in the reliability of the solders joint and IC package itself.

This article compares and evaluates the single pulse short-circuit robustness of silicon carbide (SiC) MOSFETs with linear and hexagonal cell topologies under different gate voltages, bus voltages, and case temperatures. The short-circuit failure mechanisms of the linear and hexagonal cell topologies are studied. A new switching model for gate failure and thermal runaway short-circuit failure modes is proposed and analyzed. The robustness performance of the linear and hexagonal cell topologies is compared and evaluated under the same short-circuit power for the first time, fully revealing the comprehensive impact mechanism of cell topologies on the short-circuit robustness for SiC MOSFETs.

The 1.2 kV SiC VDMOSFETs with varied JFET width (LJFET) are designed and fabricated in this study. The static and dynamic characteristics of each design are measured and compared. There is the best trade-off performance in the design of LJFET = 1.8 μm according to FOM (BV2/Ron) and FOM (Ciss/Crss). Besides, the surge capacity and evaluation for series designs are investigated under conditions of Vgs = 0 V and Vgs = −5 V. There is a best surge capacity in design of LJFET=1.2 μm, and the largest surge energy is the design of LJFET=2.0 μm. Further, the surge failure mechanisms of LJFET = 1.2 μm, 1.8 μm, and 2.0 μm under condition of Vgs = −5 V are investigated by decapsulated and FIB. Besides, the TCAD simulation was employed to theoretical analysis. The results show that the extremely high temperature was generated instantaneously under surge condition, resulting in epoxy carbonization, polysilicon melting and ILD oxide crack in failed position. Besides, the surge dissipating energy causes an instantaneous high temperature on the entire chip, resulting in aluminum remetallization. This paper would provide suggestions for device design and surge study.

Optical micro-electromechanical systems (MEMS) demand exceptional precision, yet warpage during the die attach process on printed circuit boards can compromise performance. Here, a three-dimensional thermoelastic analytical model has been developed based on Fourier heat conduction and supported beam theory. This model facilitates the in-situ calibration of solder parameters via confocal micro-Raman spectroscopy, ensuring that the simulated dynamic evolution of warpage during soldering aligns closely with digital image correlation experiments. The results show consistence with Finite Element Method with error less than 1 % and time saving more than 60 %. Orthogonal experimental analysis further reveals that substrate thickness and thermal expansion coefficient variations are the primary factors affecting warpage, while chip area has a negligible role. Given the practical challenges in reducing substrate thickness, a stress-balancing strategy incorporating an additional transition layer is proposed, which is effectively validated with a high-resolution three-dimensional profilometer. This work provides valuable insights into the predictive modeling and warpage behavior characterization, directly supporting improved mitigation strategies in the die attach process.

Graphdiyne (GDY)/two-dimensional materials (2DMs) heterostructures present unique opportunities for advanced optoelectronic and neuromorphic devices because of their exceptional electrical, optical, and structural properties. However, the traditional methods for construction of GDY/2DMs heterostructures usually lead to inferior interfaces, which seriously affects the charge separation and transport. Herein, an in situ approach for growing GDY nanowalls (NWs) on WSe2 is employed in this work. The as-prepared GDY NWs/WSe2 heterostructure exhibits self-powered broadband photodetection across 405–980 nm with a high responsivity of 2176 A/W and detectivity of 3.6 × 1012 Jones at 532 nm under 0.02 mW/cm2 illumination, significantly outperforming previously reported GDY-based devices. The efficient charge separation and strong photocarrier trapping in the GDY NWs/WSe2 heterostructure result in pronounced short-term and long-term synaptic plasticity. The nonlinear, wavelength-dependent reservoir state separation enables clear distinction of multiple pulse sequences, which shows great potential for logic processing. The successfully resolved red, green, and violet patterns, and one-shot color image recognition of a 5-letter image highlight transformative potential of GDY NWs/WSe2 device for future adaptive imaging and neuromorphic computing technologies.

Triboelectric nanogenerator (TENG), advantageous in high energy density and flexibility, is promising as a sustainable energy source but can hardly be used to power edge devices directly due to its high-voltage AC output and varying capacitive impedance. To address it, this work proposes a power-conditioning interface with a fully integrated dual synchronous switch harvesting on capacitors (D-SSHC) rectifier for triboelectric energy extraction. Furthermore, a full digital duty-cycle-based (DCB) maximum power point tracking (MPPT) algorithm is developed to optimize the energy harvesting efficiency with simple implementation and continuous tracking. Designed and fabricated in a 0.18-μm BCD process, the proposed interface can extract energy at a maximum output voltage of 70 V. According to the measurement results, it achieves 99% MPPT efficiency and an energy extraction improvement of 598% compared to a full-bridge rectifier.

The degradation mechanisms of silicon carbide (SiC) VDMOSFET and trench metal oxide semiconductor field effect transistor (MOSFET) in a 60Co gamma irradiation environment were investigated. The degradation of electrical characteristics of SiC MOSFET in different working states after irradiation with different total ionizing doses (TIDs) was explored. The defects induced during the irradiation process were studied in annealing experiments conducted after irradiation. The reasons for the degradation of SiC MOSFET caused by TID were revealed, and a prediction model of threshold voltage (Vth) shift was proposed and verified through TCAD simulation. The Vth, breakdown voltage (BV), on-resistance R, input capacitance (Ciss), output capacitance Coss, and reverse transfer capacitance C _rss were measured at different irradiation doses and annealing conditions. Experimental results indicated that the degradation of both Ron and Ciss was primarily caused by the Vth shift. As the doses increased, the shift in Vth gradually reached saturation. Similar trends to VDMOSFET were observed in trench MOSFET but with greater sensitivity to TID. In addition, MOSFETs biased at zero voltage exhibited lower shifts in Vth compared with those under high gate bias conditions. Furthermore, the increase in defects in the gate oxide during irradiation and annealing processes were calculated. Finally, a model predicting Vth shift path was established, and its accuracy and limitations were determined. This study provides valuable insights into the effect of TID on SiC MOSFETs.

Electronic components are complex systems consisting of a combination of different materials, which undergo degenerative changes over time following the second law of thermodynamics. The loss of their quality or functionality is reflected in degraded performance or behaviour of electronic components, which can lead to failures during their operation lifetime. Thus, it is crucial to understand the physics of material degradation and the factors causing it to ensure component reliability. This paper focuses on the physics-of-degradation of packaging materials, which are typically exposed the most to the environmental and operating loads. The content of this article is organised into three parts. First, an overview of the packaging technology and encapsulating materials is presented. Then, the most common degradation-causing factors and package-associated failure modes are reviewed. Lastly, the hardware requirements are discussed, including specialised sensors, measurement techniques, and Digital Twins, to capture the degradation effects and facilitate component-level health monitoring for microelectronics.

Sintered Cu nanoparticles (NPs) are promising for high-performance electronics due to their excellent thermal and electrical conductivity, as well as mechanical reliability. This study investigates the microscale mechanical behavior of sintered Cu NPs with a bimodal particle size distribution, focusing on strain rate and temperature effects. Micro-pillar compression tests were performed across strain rates of 0.0001 s⁻¹ to 0.01 s⁻¹ and temperatures from 25 °C to 350 °C. Results show that higher strain rates enhance yield strength through strain-rate hardening, while elevated temperatures lead to thermal softening and reduced mechanical stability. The Anand viscoplastic model accurately predicts these deformation behaviors. Microstructural analysis via scanning electron microscopy (SEM) and transmission electron microscopy (TEM) reveals localized deformation at 175 °C, with dislocations concentrated near the top surface and persistent porosity below, whereas at 350 °C, re-sintering and grain boundary diffusion create a denser microstructure. Phase-field fracture modeling further elucidates crack propagation, emphasizing the role of pore size and temperature. This combined experimental and modeling approach enhances understanding of viscoplastic deformation and fracture mechanisms in sintered Cu NPs, informing their use in interconnects, power electronics and thermal management systems.

While silver-based sintered materials are limited by cost and electromigration, and copper faces challenges with oxidation at high temperatures, Cu-based composite sintering materials offer promising alternative solutions. This review examines recent advances in Cu-based composite sintered materials for die-attach in power electronics packaging, focusing on their mechanical, thermal, electrical properties, and reliability. This review systematically categorizes such compounding strategies, including direct mixing, core-shell structures, and alloying, analyzing the impact on composite properties. Furthermore, the reliability of Cu-based composite sintered joints is evaluated, addressing high-temperature storage, thermal cycling, corrosion, and electrochemical migration. Challenges such as oxidation resistance, process optimization, and cost-effectiveness are discussed, together with future research directions. This work aims to support researchers in advancing Cu-based composite sintering materials research and development, broadening material options for high-temperature power electronics packaging applications.