Reliable 4H-SiC for high-power electronics and quantum photonics requires a quantitative understanding of how contact loading drives microstructure evolution and load-bearing/fracture response in epitaxial layers. Here, we integrate instrumented indentation, confocal micro-Raman residual-stress metrology, atomistic molecular dynamics (MD), and high-resolution TEM (HRTEM) to establish processing–microstructure–mechanical property linkages in chemical vapor deposition (CVD) 4H-SiC epilayers. At peak depths of 600–1050 nm, indentation promotes Palmqvist-type radial cracks and the apparent indentation toughness K_IC increases from 0.87 ± 0.08 to 1.20 ± 0.05 MPa m^1/2 with depth, consistent with plastic-zone growth and dislocation shielding. E₂(TO) Raman mapping quantifies an increase in residual stress from ∼302 ± 60 to ∼665 ± 72 MPa. It also shows that the incremental broadening of the FWHM becomes less pronounced beyond ∼750 nm, suggesting that the near-surface disorder indicator within the Raman probe volume approaches a quasi-steady level. MD captures a 4H → 3C phase transformation, amorphization beneath indenter ridges, and dislocation nucleation/growth, which HRTEM directly corroborates. The combined measurement–model–validation closed loop yields a depth-dependent relationship between residual-stress accumulation and apparent toughness, converting them into an actionable processing window: constraining penetration depth below ∼0.75 μm limits residual stress and near-surface disorder. These results provide physics-based guidance for machining and packaging of 4H-SiC epilayers and illustrate a transferable framework for brittle, anisotropic ceramics.

The paper presents a degradation for remaining useful lifetime framework for smart power stages (SPS) with an integrated temperature sensor for electronic control units (ECU). A reduced order state space model with physically meaningful time constants is derived from finite element simulations. The state space model is the core of the damage estimation of the SPS during operation. A framework for remaining useful lifetime estimation is presented simulating degradation based on an estimated mission profile for cars. Temperature cycles are extracted and used to estimate the time constant drift representing package degradation. An exemplary approach on how to integrate degradation monitoring into a lifetime approximation of the package is presented. The state space model is extended for estimator based predictions to integrate the model in future test benches for real life monitoring and remaining useful life predictions of active devices.

This study is motivated by a conceptual inconsistency in the physical interpretation of eight-chain hyperelastic theory, which arises from the combined effect of two distinct issues: the use of the marginal projection distribution p_z(|r_z|) as a surrogate for the full probability density of end-to-end distance p_r̄(r̄), and the subsequent reliance on a root mean square (RMS) approximation step in the micro–macro averaging of chain stretch. We first revisit this probabilistic mismatch by reformulating the probability density function of freely-jointed chains (FJCs) in terms of the squared end-to-end vector r², thereby restoring consistency on chain-level statistics. Building on this formulation, the micro–macro mapping averaging of chain conformational free energy is constructed directly in terms of r², leading to a one-step mean-field approximation that avoids RMS averaging. The modified probability transformation is examined by Monte Carlo sampling at the microscopic level. To account for interchain interactions, q-mean statistical description of micro tube confinement was incorporated, leading to the appearance of the general invariant I_q=λ₁^q+λ₂^q+λ₃^q. The resulting continuum constitutive model is assessed against multiaxial experimental data for several polymer networks, including vulcanized natural rubber, Entec Enflex S4035A thermoplastic elastomer, Tetra-PEG, and isoprene rubber vulcanizate. Comparisons with three existing hyperelastic strain energy formulations, the extended eight-chain, extended tube models, and the four-parameter ”comprehensive” model, demonstrate comparable phenomenological accuracy of the current model while providing a clearer and more consistent micro–macro physical interpretation of model parameters. A parametric study further illustrates how the dimensionless parameters n and q govern the shape of the macroscopic stress–strain responses. The present formulation provides a consistent theoretical basis within the scope of hyperelasticity and admits potential extensions toward more complex irreversible phenomena.

The reliability of through-glass via (TGV) interconnects is critical for advanced semiconductor packaging. This work investigates microstructural and mechanical evolution in electroplated TGV–Cu subjected to long-term aging at 250 °C. TGV samples were fabricated via laser-induced etching and double-sided copper electroplating, then aged for up to 1008 h. Nanoindentation revealed region-dependent reductions in hardness (from 2.0–2.5 GPa to below 0.5 GPa) and modulus (from 110–130 GPa to 40–90 GPa), with surface-near regions most affected. The glass substrate maintained stable mechanical properties until microcracks formed after 1008 h. EBSD quantification showed grain-size enlargement from 0.46 µm to 1.86 µm and a concurrent decrease in dislocation density. Molecular dynamics simulations of 3, 4, 5 nm grains corroborated the inverse relationship between grain size and micro-mechanical properties. A hybrid Potts-phase field model further linked grain coarsening to stress relaxation and elastic-energy minimization, revealing that as grains grow, the overall von Mises stress in the structure decreases; high-modulus grains retain relatively higher local stresses, while low-modulus, low-stress grains exhibit faster growth rates. Electrical I–V measurements confirmed stable ohmic behavior, despite a drop in insulation resistance. These integrated experimental and computational insights provide theoretical guidance for optimizing TGV interposer design and ensuring long-term operational reliability in heterogeneous integration technologies. (Figure presented.)

Cu-Ag composite sintered pastes are promising die-attach materials for wide bandgap power modules, yet their electrothermal performance is governed by 3D phase connectivity and interfacial morphology. In this work, a workflow for better predicting the thermal and electrical conductivity was presented, using 2D SEM processing, 3D reconstruction with a self-learning optimized QSGS algorithm, and electrothermal finite element simulations in COMSOL Multiphysics. A Hashin Shtrikman composition baseline, together with closed-form structure-corrected equations, was further introduced for better prediction accuracy, which enables rapid screening and microstructure-informed design of composite sintering materials for die-attach.

Silicon Carbide (SiC) MOSFETs face critical challenges in avalanche ruggedness under repetitive low-energy stresses, yet the underlying failure mechanisms and reinforcement strategies remain underexplored. This study investigates the degradation of a 1200 V/40 mΩ planar-gate SiC MOSFET through stepped single-pulse and multi-pulse unclamped inductive switching (UIS) tests. Experimental results demonstrate a 20.18 mΩ increase in on-resistance (Rdson) after 30,000 repetitive avalanche cycles, attributed primarily to bond wire aging and solder delamination. A chip-package multi-level coupled electro-thermo-mechanical model is developed, bridging carrier dynamics and package-level electro-thermo-mechanical coupled stress. The calibrated model reproduces the electrical characteristics and transient thermal response (<1.5% error) of the real device. Simulations highlight that localized electric fields exceeding 15 MV/m at bond pads and cyclic thermo-mechanical strain accelerate package-level degradation. Guided by these findings, two reinforcement strategies—increased bond-pad contact area and higher wire count—are proposed. Experimental validation over 50,000 UIS cycles demonstrates reductions in R_dson degradation of 30.1% and 36.4%, respectively, prolonging predicted fatigue life from 16,000 to 24,000 cycles. The combined experimental–simulation framework offers a scalable design methodology for extending the avalanche safe operating area of SiC MOSFETs without compromising static performance.

Sintered Cu nanoparticles (Cu NPs) are promising interconnection materials for high-temperature power electronics, yet how their authentic three-dimensional pore architecture governs microscale deformation remains unclear. Here, synchrotron nano-computed tomography (nano-CT) was combined with in-situ micropillar compression, explicit dynamic elastoplastic finite element analysis, and TEM/TKD characterization to interrogate sintered Cu NPs. The nano-CT voxel size was 45 nm, and the reconstructed volume corresponded to a cylinder 16 µm in diameter and 10 µm in height. The average sectional porosity was 12.44%, with a systematic discrepancy between two-dimensional and three-dimensional porosity quantification. During loading, the porosity decreased to 9.55% while the pore aspect ratio increased from 1.82–2.35. Finite element analysis further showed pronounced pore-adjacent stress/strain localization at the elastic–plastic transition, with local stress and equivalent plastic strain reaching 650 MPa and 1.7 × 10⁻², compared with 250 MPa and 1.1 × 10⁻³ in adjacent regions. The GND density increased by 95.9% at a compressive strain of 26%, linking pore-induced strain gradients to dislocation accumulation. These results quantitatively connect authentic three-dimensional pore architecture, local deformation localization, and dislocation-mediated strengthening in sintered Cu NPs. Highlights Synchrotron nano-CT (45 nm voxel size) reconstructed a 16 × 10 µm cylindrical volume of sintered Cu NPs and resolved the authentic 3D pore network. Sectional porosity was 12.44%, and 2D/3D quantification showed a systematic discrepancy, with porosity decreasing to 9.55% and pore aspect ratio increasing from 1.82 to 2.35 during compression. Pore-adjacent localization was quantified at the elastic–plastic transition, with local stress/PEEQ reaching 650 MPa and 1.7 × 10⁻² versus 250 MPa and 1.1 × 10⁻³ in adjacent regions. A 95.9% increase in GND density at 26% compressive strain links pore-induced strain gradients to dislocation accumulation and strain-gradient-driven strengthening.

Two-dimensional materials (2DMs)-based devices exhibit aerospace potential due to their superior properties. However, the operational reliability of 2DMs-based devices in space environments is significantly influenced by charged-particle radiation, necessitating rigorous ground-based radiation tolerance assessments. Current research on radiation effects in 2DMs is primarily experimental, yet such methodologies are inherently time-consuming, resource-intensive, and limited in throughput. To address these challenges, computational modeling and simulation techniques are increasingly being integrated with experimental characterization to accelerate materials design and unravel underlying physical mechanisms. This review systematically evaluates the state-of-the-art multiscale computational frameworks for 2DMs research, focusing on recent advancements, technical challenges, and emerging opportunities. A novel integrative approach is proposed, combining density functional theory, molecular dynamics, Monte Carlo, finite element analysis, and machine learning techniques. Particular emphasis is placed on addressing challenges in multiscale modeling, including accurate representation of complex phenomena across spatial and temporal scales under extreme environmental conditions. Conversely, opportunities for enhancing predictive capabilities are highlighted, with implications for expediting materials discovery in electronics, photonics, energy storage, catalysis, and nanomechanical systems. This comprehensive survey provides a strategic roadmap for future research directions in multiscale computational modeling of 2DMs, emphasizing interdisciplinary methodologies that bridge atomistic simulations with macroscale engineering applications. The insights presented herein aim to advance the development of radiation-hardened 2DMs-based devices for next-generation aerospace systems.

Particle morphology is a critical structural variable in pressure-assisted sintering because it controls packing, pore topology, interparticle bonding and load transfer. Here, copper (Cu) was used as a model system to examine how monomodal spherical, bimodal spherical and flake-shaped particle assemblies, processed under identical conditions, form porous structures with distinct mechanical responses. Micro-pillar compression reveals low effective elastic moduli of 7.5–12.5 GPa and high yield strengths of 403–450 MPa. The deformation pathways are strongly morphology dependent. The monomodal structure accommodates strain through distributed pore collapse and particle deformation, leading to progressive densification hardening. The bimodal structure exhibits size-partitioned deformation, with large particles forming the main load-bearing backbone and smaller particles accommodating local rearrangement, embedding and shear compaction. The flake-shaped structure undergoes geometry-guided deformation, where extended face-to-face bonding enhances local load bearing, while inter-flake misalignment concentrates strain and promotes shear localization. Post-compression transmission electron microscopy (TEM) and transmission Kikuchi diffraction (TKD) analyses link these modes to pore collapse, neck deformation and grain-scale strain accommodation. TKD further gives average Geometrically Necessary Dislocations (GND) densities of 4.36×10¹⁴ m⁻², 3.69×10¹⁴ m⁻² and 4.11×10¹⁴ m⁻² for the monomodal, bimodal and flake-shaped structures, respectively. Molecular dynamics (MD) simulations reproduce the corresponding strain-localization patterns and reveal morphology-controlled load-transfer pathways dominated by Shockley partial dislocations. These results establish particle morphology as a design parameter for tuning stiffness, strength and damage tolerance in sintered porous metals.

The rapid growth of generative Artificial Intelligence (AI), automotive electrification and Internet of Things (IoT) is driving an unprecedented demand for high-performance Integrated Circuits (ICs), projected to push the semiconductor industry to a $1 trillion business by 2030 (Burkacky et al., 2022; PWC, 2025). This drove the adoption of advanced process (FinFET, Gate-All-Around, Forksheet, CFET, Backside Power Delivery Network) and 3D package technologies (chiplets, Heterogeneous Integration, Co-packaged Optics). Unfortunately, component stacking in 3D ICs such as Package-on-Package (PoP) products creates an optical barrier during Electrical Fault Isolation (EFI). This paper presents a novel Failure Analysis (FA) hardware and sample preparation solution that enables System-Level FA on mobile System-on-a-Chip (SoC) PoP devices, where the DRAM is stacked atop the logic controller device. The primary challenge in performing EFI on the bottom die is providing direct line-of-sight (LoS) access while preserving the top DRAM functionality through extremely small interconnects called Through Interposer Vias (TIVs). For the first time, this groundbreaking hardware solution overcomes the challenge of connecting a DRAM atop the SoC silicon, utilizing the smallest possible interposer pin pitch (∼210 um) and advanced DRAM card design that incorporates stringent design rules to enable up to 6.3 Gbps using a DDR training test and runs standard Android stress applications. The results of the FA hardware solution for SLT platform will be discussed, together with several FA use cases that were enabled through this innovative solution. Lastly, this paper will discuss the limitations of this hardware, together with opportunities for improvement and further work. This novel solution paves the way for the failure analysis of 3D IC devices on a system level platform, which are utilized not only in mobile applications, but also for cloud, server, and quantum computing ICs assembled in complex packages.

Higher switching speeds and power densities enabled by SiC MOSFETs make accurate, time-resolved junction-Temperature (Tj) estimation under realistic switching conditions increasingly important for performance validation, thermal design, and reliability assessment. This work presents an electro-Thermal co-simulation framework for SiC MOSFET double-pulse testing, combining measured switching waveforms with a compact thermal network (Cauer model) to translate transient switching-loss energy into (Tj) evolution. A Peak-Power-Threshold (PPT) method is introduced to robustly identify the switching interval and compute instantaneous power and switching energies (Eon, Eoff) from experimental data, enabling consistent comparison between measurement and simulation across few operating points. The proposed approach links dynamic loss extraction to junction-Temperature estimation in a unified workflow, supporting more reliable interpretation of double-pulse tests and improving confidence in electro-Thermal estimation for high-performance SiC power converters.

Finite element (FE) simulations of structures and materials are becoming increasingly accurate, but also more computationally expensive as a collateral result. This development occurs in parallel with a growing demand for data-driven design. To reconcile the two, a robust and data-efficient optimization method called Bayesian optimization (BO) has been previously established as a technique to optimize expensive objective functions. The mesh width of an FE model can be exploited to evaluate an objective at a lower or higher fidelity (cost & accuracy) level, which is the domain of multi-fidelity BO (MFBO) applications. However, BO and MFBO are usually not directly compared in the literature. Moreover, sampling quality and assessing design parameter sensitivity are often underrepresented parts of data-driven design. This paper combines global sensitivity analysis and (MF) BO into a novel, efficient Bayesian data-driven framework. We compare the performance of BO with that of MFBO by maximizing the energy absorption (EA) problem of spinodoid cellular structures. The findings show that similar or better designs are suggested by MFBO with 16% fewer expensive objective evaluations compared to BO when maximizing the EA. The results, which are made open-source, serve to support the utility of multi-fidelity techniques across expensive data-driven design problems.

Sintered porous Cu contains a heterogeneous particle-neck-pore architecture whose deformation depends strongly on loading mode. In this study, porous Cu structures prepared from small particles (184 nm) and large particles (1451 nm) were examined using micropillar compression, micro-cantilever bending, scanning electron microscopy (SEM), transmission electron microscopy (TEM), and molecular dynamics (MD) simulations. Under compression, the large-particle structure exhibited a higher apparent elastic modulus (14.5 ± 0.9 GPa) than the small-particle structure (12.7 ± 0.5 GPa), whereas the small-particle structure showed an approximately 80% higher yield strength (364 ± 58 versus 202 ± 71 MPa). In contrast, the large-particle structure exhibited an approximately 245% higher conditional fracture toughness (5.56 ± 0.14 versus 1.61 ± 0.16 MPa⋅m^1/2) and 1270% higher total bending work (8823 ± 1245 versus 644 ± 164 pJ). Microstructural analyses revealed that the refined particle-neck network accommodated compression through distributed pore compaction, neck deformation, and dislocation accumulation, suppressing strain localization. The coarser network promoted intraparticle slip and interfacial sliding under compression, while enhancing remaining-ligament continuity and neck bridging during crack propagation. MD simulations reproduced these distinct compressive responses and defect-evolution characteristics. These findings provide guidance for optimizing particle-neck-pore architectures in reliable sintered Cu interconnects.

The evolution in modern-day electronics extends beyond miniaturization and significantly increases the number of power cycles operating with low temperature swings (few tens of degrees). This shift has raised the reliability requirements and expectations for electronics systems to last longer. The transition of vehicles and autonomous systems to zonal architectures, driven by electrification, has increased power-on hours of electronic components, leading to higher system complexity and more challenging reliability testing. Currently, standardized stress- based tests and predictive models have constraints, as they are designed for large temperature swings and are inaccurate for evaluating low T conditions. Additionally, the damage caused by Δ millions of low thermal swings is less explored in simulation and qualification, making it important to analyze the influence of low ΔT on solder joints to understand field reliability risks.An Arduino-based testing setup was developed to apply active thermal cycles to WLCSP40 using relay-controlled switching with 6-second cycles. Samples were tested from 50k to 800k cycles to analyze the long-term damage accumulation under such conditions. In addition to experiments, a thermomechanical simulation in COMSOL incorporated ΔT values obtained from thermal camera characterization to establish realistic boundary conditions. It helps to correlate experimental results and identify critical locations within the solder joints where damage is most likely to occur.Cumulative plastic strain analysis and cross-sectional imaging revealed cracks in the solder bulk at 40 °C, demonstrating microstructural fatigue under low ΔT cycling. Furthermore, based on strain per cycle values, the results exhibit how the active and passive thermal cycles differ.

Pressureless sintered Ag pastes are promising die-attach materials for power electronics, yet practical sintering-profile optimization still relies heavily on trial-and-error, and the link from thermal kinetics to fracture-relevant microstructure and strength remains insufficiently established. In this work, a thermal-kinetics-guided workflow was developed to design paste-specific pressureless sintering profiles for two commercial Ag pastes (a spherical-particle paste and a flake-based paste) and to interpret the resulting strength–fracture response using SEM-based, heterogeneity-aware learning. Multi-heating-rate TGA was used to define the conversion fraction (α), while DSC was used to identify the dominant thermal-event window and extract the characteristic peak temperature for Arrhenius pairing. The TGA-defined conversion evolution was then modeled using a JMAK/Avrami form with Arrhenius temperature dependence to predict the isothermal holding time required to reach a target conversion at a selected dwell temperature. Relative to supplier-recommended profiles, the optimized profiles increased die-shear strength by 35% for the spherical-particle paste and by 206% for the flake-based paste, and promoted a fracture-mode transition from interfacial debonding toward mixed/cohesive fracture. Pearson/Ridge baselines and attention-based multiple-instance learning (MIL) linked strength and fracture-mode distribution to porosity/connectivity-related descriptors; paste-wise normalization mitigated paste-specific baselines and enabled MIL to reveal profile-induced microstructure–performance co-variation. Overall, this study establishes a practical workflow that couples thermal-kinetics-guided profile design with mechanical and fractographic validation and interpretable microstructure–property attribution, supporting mechanism-informed optimization of pressureless sintered Ag die-attach pastes.