As 2.5D/3D advanced packaging moves toward higher interconnect density, glass substrates are attractive for their electrical performance and dimensional stability. However, high aspect ratio, fine pitch through-glass vias (TGVs) are prone to thermo-mechanical failures under long-term thermal shock, and microscale reliability assessment is hindered by costly microstructural characterization and the lack of models capturing long-term microstructural evolution and property degradation. Here, fully copper-filled TGV-Cu structures were fabricated on Schott AF32 glass and subjected to thermal-shock cycling from - 40 ℃ to 125 ℃ (0, 700, 1400, and 2100 cycles). Results show a non-monotonic, location-dependent hardness evolution with pronounced heterogeneity, where the mid-via region exhibits stronger late-stage softening by nanoindentation. EBSD shows grain diameter increases from 0.61 μm to 0.91 μm, while GND density decreases by recovery and then re-accumulates preferentially near the via bottom, evidencing competition between grain-growth softening and dislocation hardening. Hybrid Potts-phase field simulations further predict continuous grain growth and stress relaxation (declining von Mises stress) inside the via; including the glass substrate and interface constraints raises the stress level but preserves the relaxation trend. Moreover, the phase field simulations results of equivalent plastic strain (PEEQ) reveal progressively intensified cyclic plastic localization near the top/bottom caps (Cu/glass intersections), providing mechanistic support for cracking localized at the via mouths.

Reliable 4H-SiC for high-power electronics and quantum photonics requires a quantitative understanding of how contact loading drives microstructure evolution and load-bearing/fracture response in epitaxial layers. Here, we integrate instrumented indentation, confocal micro-Raman residual-stress metrology, atomistic molecular dynamics (MD), and high-resolution TEM (HRTEM) to establish processing–microstructure–mechanical property linkages in chemical vapor deposition (CVD) 4H-SiC epilayers. At peak depths of 600–1050 nm, indentation promotes Palmqvist-type radial cracks and the apparent indentation toughness K_IC increases from 0.87 ± 0.08 to 1.20 ± 0.05 MPa m^1/2 with depth, consistent with plastic-zone growth and dislocation shielding. E₂(TO) Raman mapping quantifies an increase in residual stress from ∼302 ± 60 to ∼665 ± 72 MPa. It also shows that the incremental broadening of the FWHM becomes less pronounced beyond ∼750 nm, suggesting that the near-surface disorder indicator within the Raman probe volume approaches a quasi-steady level. MD captures a 4H → 3C phase transformation, amorphization beneath indenter ridges, and dislocation nucleation/growth, which HRTEM directly corroborates. The combined measurement–model–validation closed loop yields a depth-dependent relationship between residual-stress accumulation and apparent toughness, converting them into an actionable processing window: constraining penetration depth below ∼0.75 μm limits residual stress and near-surface disorder. These results provide physics-based guidance for machining and packaging of 4H-SiC epilayers and illustrate a transferable framework for brittle, anisotropic ceramics.

The reliability of through-glass via (TGV) interconnects is critical for advanced semiconductor packaging. This work investigates microstructural and mechanical evolution in electroplated TGV–Cu subjected to long-term aging at 250 °C. TGV samples were fabricated via laser-induced etching and double-sided copper electroplating, then aged for up to 1008 h. Nanoindentation revealed region-dependent reductions in hardness (from 2.0–2.5 GPa to below 0.5 GPa) and modulus (from 110–130 GPa to 40–90 GPa), with surface-near regions most affected. The glass substrate maintained stable mechanical properties until microcracks formed after 1008 h. EBSD quantification showed grain-size enlargement from 0.46 µm to 1.86 µm and a concurrent decrease in dislocation density. Molecular dynamics simulations of 3, 4, 5 nm grains corroborated the inverse relationship between grain size and micro-mechanical properties. A hybrid Potts-phase field model further linked grain coarsening to stress relaxation and elastic-energy minimization, revealing that as grains grow, the overall von Mises stress in the structure decreases; high-modulus grains retain relatively higher local stresses, while low-modulus, low-stress grains exhibit faster growth rates. Electrical I–V measurements confirmed stable ohmic behavior, despite a drop in insulation resistance. These integrated experimental and computational insights provide theoretical guidance for optimizing TGV interposer design and ensuring long-term operational reliability in heterogeneous integration technologies. (Figure presented.)

Power electronics devices, pivotal in advancing electronic system technology, are essential for energy saving, enhancing power control efficiency, reducing noise, and minimizing size and volume. The evolution of power modules is based on innovative packaging structures, technologies, and materials. This article provides a comprehensive review of inorganic nonmetallic packaging materials and technologies in power electronics packaging. It first analyzes the packaging structures and trends of power electronics. The article then discusses inorganic nonmetallic encapsulants such as cement and glass in detail. It also reviews traditional ceramic substrates and elaborates on the advantages of multilayer ceramic technologies, including low-temperature co-fired ceramics, as substrates, while looking forward to the commercialization of inorganic composite substrates such as SiCp/Al matrix composites and diamond. Subsequently, the article overviews inorganic nonmetallic fillers for thermal interface materials, emphasizing the application of two-dimensional materials such as graphene and boron nitride, and introduces inorganic nonmetallic phase change materials. Finally, it explores the application and future development trends of inorganic nonmetallic materials in embedded packaging technologies.

Reducing parasitic parameters and thermal resistance is critical for advancing power electronic devices. This article designs and evaluates the three printed circuit board (PCB) embedded 1200 V SiC mosfet half-bridge packaging cells, where the traditional wire bonding process is replaced by a redistribution layer (RDL) technique. A comprehensive evaluation of their electrical performance, thermal management, and mechanical performance is conducted. The three solutions that employ panel, active metal brazing (AMB), and lead—frame carriers, are developed through a streamlined process that includes die attach, molding, drilling, plating, and etching. This packaging approach readily reduces the parasitic inductance to below 5 nH. By utilizing a single-layer RDL with mutual inductance cancellation, the power loop inductance is reduced to as low as 2.4 nH (at 10 MHz), and the gate loop inductance to 1.57 nH (at 10 MHz). The junction-to-case thermal resistances of the three solutions are 1.88, 1.03, and 0.73 K/W, respectively. Compared with the other two packaging cells, the cell selecting AMB as a carrier reduces SiC mosfet operational stress and deformation by approximately 34% and 75%. The lead—frame carrier offers superior thermal dissipation for potential TO package replacement in half-bridge topologies, while the panel solution is promising for dual-sided cooling applications. With low thermal resistance, minimal stress, and excellent backside electrical insulation, the packaging cell with an AMB carrier is ideally suited for integration with heatsinks in traction inverters.

Silicon carbide (SiC) power devices exhibit superior thermal conductivity and excellent high-temperature stability, making them promising for high-power applications under extreme environments. However, ensuring long-term reliability, especially for devices packaged with glass encapsulant, remains a significant challenge. This paper introduces a high-temperature step stress aging test as a highly accelerated life testing method to evaluate the reliability of SiC Schottky diodes packaged with glass encapsulants compared to traditional plastic-packaged counterparts. In this test, diodes undergo incremental thermal stress from 50 °C to 300 °C, increasing by 50 °C per step and held for 168 hours per step to simulate prolonged thermal exposure. Finite element simulations were also performed at 300 °C to analyze stress distributions in various packaging configurations. Post-aging results demonstrate the effectiveness of this accelerated method for rapidly assessing device degradation, providing valuable reliability insights for applications in extreme thermal environments such as aerospace power systems.

Sintered nano-copper (Cu) improves the thermal performance of SiC MOSFET Fan-Out Panel-Level Packaging (FOPLP), a widely adopted method for miniaturizing electronic systems and modules. This study presented, for the first time, the prototyping and characterization of a 1.2 kV SiC MOSFET FOPLP half-bridge power module using sintered nano-Cu die attachment (FOPLPCu), and compared it with a reference module using conductive Ag adhesive interconnects (FOPLP_Ag). Thermal, mechanical, and electrical co-simulations proved that FOPLPCu exhibited superior performances with lower thermal resistance, power loop parasitic inductance, and thermal deformation, achieving values of 0.14 °C/W (with double-sided cooling), 3.15 nH (@100 kHz), and 9.05e-5 m, respectively. In contrast, FOPLP_Ag showed higher values of 0.24 °C/W, 3.27 nH, and 1.04e-4 m. It is worth noting that due to the higher elastic modulus of sintered nano Cu, FOPLPCu experienced increased thermal stress. The internal structure analysis of the packaged devices, conducted using CSAM, showed that both FOPLPCu and FOPLP_Ag had well-formed interconnections, with no signs of delamination in the EMC, RDL, or interconnect layers. Thermal testing showed that FOPLPCu achieved a single-side thermal resistance of 1.95 °C/W, representing a 22% improvement compared to FOPLP_Ag's 2.5 °C/W. Electrical testing further demonstrated that FOPLPCu had lower on-state resistance compared to FOPLP_Ag, while maintaining comparable breakdown voltage, threshold voltage, and body diode forward voltage drop.

Investigating the interconnection and strengthening mechanisms of die-attach layers is instrumental for advancing die attach process toward low-pressure and, ultimately, pressureless sintering while maintaining reliability. This study compares the microstructure and micromechanical heterogeneity of the pressure-assisted and pressureless regions in SiC die attach to elucidate the interconnection and strengthening mechanisms. Recrystallized grains make up 71.7 % of the pressureless region, markedly lower than the approximately 90 % observed in the pressure-assisted region, resulting in a higher porosity in the former. Evidence of both continuous dynamic recrystallization and discontinuous dynamic recrystallization is identified throughout the sintered layer. Microhardness reveals that the pressureless zone exhibits a hardness of 0.373 GPa, significantly lower than left (0.745 GPa) and right (1.832 GPa) of pressure-assisted region. All three regions share an average grain size of 400 ± 50 nm, and geometrically necessary dislocation density in pressureless zone exceeds that in pressure-assisted areas, neither of which can account for the difference in micromechanical performance. In contrast, the statistically stored dislocation (SSD) densities on the left and right of the pressure-assisted region are approximately 4.74 × 10¹⁴ m⁻² and 2.88 × 10¹⁵ m⁻², respectively—substantially higher than the 2.88 × 10¹⁴ m⁻² measured in the pressureless region. Collectively, these findings demonstrate that dislocation strengthening, and particularly SSD density, constitutes the dominant strengthening mechanism in silver sintered layers. This work not only provides new insights for enhancing reliability under low-pressure and pressureless sintering but also establishes a theoretical foundation for optimizing sintering material formulations.