Although silver sintering is widely used in die attach, its reliability under low-pressure and pressureless sintering conditions remains a challenge, and the degradation mechanism needs to be addressed urgently. This study investigates the degradation mechanisms of silver sintered die attach subjected to thermal shock (TS) (−45 °C to 125 °C), revealing its microstructural evolution, degradation of mechanical properties, and pore dynamics. After 1500 cycles, the average porosity did not decrease and remained at approximately 10%, but the porosity distribution exhibited significant heterogeneity, forming three characteristic regions of high porosity, low porosity, and crack regions. With the porosity evolution, the grain size increased by a factor of 2.1–2.8, with the largest grain sizes in the crack region, and the recrystallization fraction decreased significantly, from 89.6 % to a range of 37.3 %–72.1 %. Additionally, the combination with the decrease in both statistically stored dislocation density and total dislocation density reveals a decline in hardness and yield strength of silver sintered layer from 1.05 GPa and 326 MPa to 0.92 GPa and 231 MPa, respectively, gradually diminishing their ability to impede pore migration and merging. Thermal-mechanical coupling simulations based on the actual porous structure images show that the mismatch in the coefficient of thermal expansion induces alternating tensile and compressive thermal stresses, driving pore evolution and crack propagation. The kinetic Monte Carlo (KMC) Potts model based on Kawasaki dynamics combined with pore conservation can effectively predict the long-term pore evolution in this case. These findings provide important guidance for optimizing the sintering process and improving the application of silver sintering materials in high-reliability electronic packaging.

Pressureless sintered Ag pastes are promising die-attach materials for power electronics, yet practical sintering-profile optimization still relies heavily on trial-and-error, and the link from thermal kinetics to fracture-relevant microstructure and strength remains insufficiently established. In this work, a thermal-kinetics-guided workflow was developed to design paste-specific pressureless sintering profiles for two commercial Ag pastes (a spherical-particle paste and a flake-based paste) and to interpret the resulting strength–fracture response using SEM-based, heterogeneity-aware learning. Multi-heating-rate TGA was used to define the conversion fraction (α), while DSC was used to identify the dominant thermal-event window and extract the characteristic peak temperature for Arrhenius pairing. The TGA-defined conversion evolution was then modeled using a JMAK/Avrami form with Arrhenius temperature dependence to predict the isothermal holding time required to reach a target conversion at a selected dwell temperature. Relative to supplier-recommended profiles, the optimized profiles increased die-shear strength by 35% for the spherical-particle paste and by 206% for the flake-based paste, and promoted a fracture-mode transition from interfacial debonding toward mixed/cohesive fracture. Pearson/Ridge baselines and attention-based multiple-instance learning (MIL) linked strength and fracture-mode distribution to porosity/connectivity-related descriptors; paste-wise normalization mitigated paste-specific baselines and enabled MIL to reveal profile-induced microstructure–performance co-variation. Overall, this study establishes a practical workflow that couples thermal-kinetics-guided profile design with mechanical and fractographic validation and interpretable microstructure–property attribution, supporting mechanism-informed optimization of pressureless sintered Ag die-attach pastes.

Accurate characterization and calculation of the interfacial stresses are of key importance for the optimization of the chip sintering process and the evaluation of the long-term reliability of the chip interconnect. In this study, the pioneering application of confocal Raman spectroscopy for the accurate, rapid, and nondestructive characterization of interfacial stresses at the interconnections of silicon carbide chips was undertaken. Silicon carbide chips (5 mm ∗ 5 mm) were mounted to active metal brazing substrates by pressure-assisted sintering using copper nanoparticles. Subsequently, finite element simulations were used to model the thermally induced deformation and stress in the SiC chip. The thermally induced warpage of the SiC chip was then measured using interferometry. Finally, confocal Raman spectroscopy was employed to measure the interface stress distribution at the SiC sintered copper interface. The results showed that finite element simulations could not accurately assess the thermally induced deformation and stress in the SiC chip. The proposed method based on confocal Raman spectroscopy for testing chip interconnection interface stresses achieved an excellent balance between accuracy, non-contact measurement, and non-destructive testing. The residual stress at the backside interface of the SiC chip was concentrated in the central region of the chip, with compressive stress values ranging from -139 MPa to -165 MPa. Theoretically, this study provides a new framework for modeling and researching the reliability of electronic packaging interfaces.

Sintered nano-copper (Cu) improves the thermal performance of SiC MOSFET Fan-Out Panel-Level Packaging (FOPLP), a widely adopted method for miniaturizing electronic systems and modules. This study presented, for the first time, the prototyping and characterization of a 1.2 kV SiC MOSFET FOPLP half-bridge power module using sintered nano-Cu die attachment (FOPLPCu), and compared it with a reference module using conductive Ag adhesive interconnects (FOPLP_Ag). Thermal, mechanical, and electrical co-simulations proved that FOPLPCu exhibited superior performances with lower thermal resistance, power loop parasitic inductance, and thermal deformation, achieving values of 0.14 °C/W (with double-sided cooling), 3.15 nH (@100 kHz), and 9.05e-5 m, respectively. In contrast, FOPLP_Ag showed higher values of 0.24 °C/W, 3.27 nH, and 1.04e-4 m. It is worth noting that due to the higher elastic modulus of sintered nano Cu, FOPLPCu experienced increased thermal stress. The internal structure analysis of the packaged devices, conducted using CSAM, showed that both FOPLPCu and FOPLP_Ag had well-formed interconnections, with no signs of delamination in the EMC, RDL, or interconnect layers. Thermal testing showed that FOPLPCu achieved a single-side thermal resistance of 1.95 °C/W, representing a 22% improvement compared to FOPLP_Ag's 2.5 °C/W. Electrical testing further demonstrated that FOPLPCu had lower on-state resistance compared to FOPLP_Ag, while maintaining comparable breakdown voltage, threshold voltage, and body diode forward voltage drop.

Reducing parasitic parameters and thermal resistance is critical for advancing power electronic devices. This article designs and evaluates the three printed circuit board (PCB) embedded 1200 V SiC mosfet half-bridge packaging cells, where the traditional wire bonding process is replaced by a redistribution layer (RDL) technique. A comprehensive evaluation of their electrical performance, thermal management, and mechanical performance is conducted. The three solutions that employ panel, active metal brazing (AMB), and lead—frame carriers, are developed through a streamlined process that includes die attach, molding, drilling, plating, and etching. This packaging approach readily reduces the parasitic inductance to below 5 nH. By utilizing a single-layer RDL with mutual inductance cancellation, the power loop inductance is reduced to as low as 2.4 nH (at 10 MHz), and the gate loop inductance to 1.57 nH (at 10 MHz). The junction-to-case thermal resistances of the three solutions are 1.88, 1.03, and 0.73 K/W, respectively. Compared with the other two packaging cells, the cell selecting AMB as a carrier reduces SiC mosfet operational stress and deformation by approximately 34% and 75%. The lead—frame carrier offers superior thermal dissipation for potential TO package replacement in half-bridge topologies, while the panel solution is promising for dual-sided cooling applications. With low thermal resistance, minimal stress, and excellent backside electrical insulation, the packaging cell with an AMB carrier is ideally suited for integration with heatsinks in traction inverters.

Investigating the interconnection and strengthening mechanisms of die-attach layers is instrumental for advancing die attach process toward low-pressure and, ultimately, pressureless sintering while maintaining reliability. This study compares the microstructure and micromechanical heterogeneity of the pressure-assisted and pressureless regions in SiC die attach to elucidate the interconnection and strengthening mechanisms. Recrystallized grains make up 71.7 % of the pressureless region, markedly lower than the approximately 90 % observed in the pressure-assisted region, resulting in a higher porosity in the former. Evidence of both continuous dynamic recrystallization and discontinuous dynamic recrystallization is identified throughout the sintered layer. Microhardness reveals that the pressureless zone exhibits a hardness of 0.373 GPa, significantly lower than left (0.745 GPa) and right (1.832 GPa) of pressure-assisted region. All three regions share an average grain size of 400 ± 50 nm, and geometrically necessary dislocation density in pressureless zone exceeds that in pressure-assisted areas, neither of which can account for the difference in micromechanical performance. In contrast, the statistically stored dislocation (SSD) densities on the left and right of the pressure-assisted region are approximately 4.74 × 10¹⁴ m⁻² and 2.88 × 10¹⁵ m⁻², respectively—substantially higher than the 2.88 × 10¹⁴ m⁻² measured in the pressureless region. Collectively, these findings demonstrate that dislocation strengthening, and particularly SSD density, constitutes the dominant strengthening mechanism in silver sintered layers. This work not only provides new insights for enhancing reliability under low-pressure and pressureless sintering but also establishes a theoretical foundation for optimizing sintering material formulations.

This study investigates the size-dependent mechanical behavior and deformation mechanisms of sintered copper (Cu) nanoparticles (NPs) through micro-pillar (2–6 μm diameter) compression tests, scanning electron microscopy (SEM), transmission electron microscopy (TEM), transmission Kikuchi diffraction (TKD) analysis and molecular dynamics (MD) simulations. In-situ micro-pillar compression tests reveal a 25.9% reduction in yield strength (812 ± 64 MPa to 643 ± 47 MPa) with increasing pillar size, attributed to dislocation starvation in smaller pillars and porosity-driven strain localization in larger ones. TKD quantifies dynamic grain refinement (24.9% reduction in grain size) and geometrically necessary dislocation (GND) density escalation (74.8%), driven by stress gradients and grain boundary-mediated plasticity. Nanoindentation-derived elastic modulus (48.3 ± 11.1 GPa) exceeds micropillar values (29.5–33.9 GPa), reflecting substrate constraints in bulk testing. Microstructural analysis identifies a transition from shear banding in high-porosity pillars to uniform plasticity in denser systems, mediated by texture evolution (Brass/S components) and Schmid factor redistribution (62% increase in high-slip-activity grains). MD simulations of pressure-sintered Cu NPs elucidate atomic-scale mechanisms: dislocation nucleation at sintering necks, pore collapse-induced strain localization, and grain boundary sliding. These findings establish a multiscale framework linking porosity, grain refinement, and dislocation dynamics to mechanical performance, emphasizing microstructural optimization for enhanced reliability in microelectronic applications. The integration of MD simulations bridges atomic-scale mechanisms to microscale deformation, providing actionable insights for tailoring sintered Cu NPs via reduced porosity and controlled grain boundary architectures.

Power electronics devices, pivotal in advancing electronic system technology, are essential for energy saving, enhancing power control efficiency, reducing noise, and minimizing size and volume. The evolution of power modules is based on innovative packaging structures, technologies, and materials. This article provides a comprehensive review of inorganic nonmetallic packaging materials and technologies in power electronics packaging. It first analyzes the packaging structures and trends of power electronics. The article then discusses inorganic nonmetallic encapsulants such as cement and glass in detail. It also reviews traditional ceramic substrates and elaborates on the advantages of multilayer ceramic technologies, including low-temperature co-fired ceramics, as substrates, while looking forward to the commercialization of inorganic composite substrates such as SiCp/Al matrix composites and diamond. Subsequently, the article overviews inorganic nonmetallic fillers for thermal interface materials, emphasizing the application of two-dimensional materials such as graphene and boron nitride, and introduces inorganic nonmetallic phase change materials. Finally, it explores the application and future development trends of inorganic nonmetallic materials in embedded packaging technologies.

With more and more people adopting wearable fitness devices to help them carry out physical activities more regularly, the market analysis reports a relatively high abandonment rate after six months of usage. This article aims to contribute to consumer study in fitness wearable technology by understanding the underlying determinants of consumer’s continuance intention to use wearable fitness devices (e.g., fitness trackers), and proposing a few suggestions to fitness wearable companies and designers for further product development. This research article consists of two empirical studies. In the first study, we propose a research model that is based on the expectation-confirmation model and integrates two extra factors, which are 'technology innovativeness’ and 'eHealth literacy’. The data collection is done via online surveys. The second study is intended to design upon the findings from the first study, during which we did arrange an offline education intervention for student participants and conduct a 2 × 2 experimental study. For both studies, we use quantitative methods to analyse data and draw conclusions. From the first study, we found that users’ technology innovativeness and eHealth literacy will indirectly influence their continuous intention to use wearable fitness devices. The second study reveals that male consumers tend to increase their continuance intention to use wearable fitness devices when their eHealth literacy has been enhanced by training. To sum up, the value of this article lies in two aspects. First, it is the first study in the field of fitness wearable technology (FWT) to learn how consumer behaviour will be influenced by a person’s eHealth literacy. Second, our study goes further to investigate to what extent the improvement of eHealth literacy will influence consumer’s continuous intention.