In-Situ Confocal Raman Spectroscopy Assisted Interfacial Residual Stress Characterization in SiC Chip Sintered on AMB Substrate with Nanocopper Paste
Xuyang Yan (Fudan University)
Zhoudong Yang (Fudan University)
Chao Gu (Fudan University)
Tiancheng Tian (Fudan University, Boschman Advanced Packaging Technology)
Xuejun Fan (Lamar University, TU Delft - Electronic Components, Technology and Materials)
Guoqi Zhang (TU Delft - Electronic Components, Technology and Materials)
Jiajie Fan (TU Delft - Electronic Components, Technology and Materials, Fudan University, Shanghai Engineering Technology Research Center for SiC Power Device)
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Abstract
Accurate characterization and calculation of the interfacial stresses are of key importance for the optimization of the chip sintering process and the evaluation of the long-term reliability of the chip interconnect. In this study, the pioneering application of confocal Raman spectroscopy for the accurate, rapid, and nondestructive characterization of interfacial stresses at the interconnections of silicon carbide chips was undertaken. Silicon carbide chips (5 mm ∗ 5 mm) were mounted to active metal brazing substrates by pressure-assisted sintering using copper nanoparticles. Subsequently, finite element simulations were used to model the thermally induced deformation and stress in the SiC chip. The thermally induced warpage of the SiC chip was then measured using interferometry. Finally, confocal Raman spectroscopy was employed to measure the interface stress distribution at the SiC sintered copper interface. The results showed that finite element simulations could not accurately assess the thermally induced deformation and stress in the SiC chip. The proposed method based on confocal Raman spectroscopy for testing chip interconnection interface stresses achieved an excellent balance between accuracy, non-contact measurement, and non-destructive testing. The residual stress at the backside interface of the SiC chip was concentrated in the central region of the chip, with compressive stress values ranging from -139 MPa to -165 MPa. Theoretically, this study provides a new framework for modeling and researching the reliability of electronic packaging interfaces.