Power electronics devices, pivotal in advancing electronic system technology, are essential for energy saving, enhancing power control efficiency, reducing noise, and minimizing size and volume. The evolution of power modules is based on innovative packaging structures, technologies, and materials. This article provides a comprehensive review of inorganic nonmetallic packaging materials and technologies in power electronics packaging. It first analyzes the packaging structures and trends of power electronics. The article then discusses inorganic nonmetallic encapsulants such as cement and glass in detail. It also reviews traditional ceramic substrates and elaborates on the advantages of multilayer ceramic technologies, including low-temperature co-fired ceramics, as substrates, while looking forward to the commercialization of inorganic composite substrates such as SiCp/Al matrix composites and diamond. Subsequently, the article overviews inorganic nonmetallic fillers for thermal interface materials, emphasizing the application of two-dimensional materials such as graphene and boron nitride, and introduces inorganic nonmetallic phase change materials. Finally, it explores the application and future development trends of inorganic nonmetallic materials in embedded packaging technologies.

Silicon carbide (SiC) devices have shown definite advantages over Si counterparts in high-temperature, high-voltage, and high-frequency applications. To fully exploit the potentiality of SiC devices in high temperatures, die-attach materials that can withstand high temperatures for a long time are required in the power electronics packaging. In this article, the high-temperature die-attach materials, such as high-temperature solders and transient liquid-phase bonding materials, were reviewed first. Then, metallic (mainly Ag and Cu) nanoparticles (NPs) sintering technologies were thoroughly overviewed. The metallic NPs sintering materials, metallic NPs sintering process, and interface and reliability were analyzed, respectively. Finally, the challenges and outlook of promising Cu NPs sintering technology were discussed.

Nowadays, fan-out package is regarded as one of the latest and most potential technologies because it possesses lower cost, thinner profile, and better electrical performance and thermal performance. However, thermally induced warpage in the molding process is a critical issue due to the larger wafer or panel size, the shrinkage of epoxy mold compound (EMC) during the curing stage, and the mismatch of coefficient of thermal expansion (CTE) among the constituent materials during the cooling stage, which needs to be controlled effectively for successful subsequent process of the fan-out package. In this paper, a novel $320 x 320$-mm² panel-level fan-out package based on ``Die Last'' process is developed. A coreless substrate with redistribution layer is fabricated and bonded onto a low-CTE and high-glass-transition-temperature (Tg) FR4 carrier through thermal release film. The thermally induced warpage issue in the molding process is investigated. A warpage simulation method is presented and verified by Shadow Moiré experiment. The error between the simulation and experimental results is about 4.8%. For the warpage optimization analysis, the effect of geometry structure on the warpage is first investigated by the design of simulation approach. Full factor experiment is conducted, and Minitab statistical software is utilized to analyze the effect of the geometry structure on warpage. It is found that decreasing die thickness and molding thicker EMC can effectively decrease the warpage. Then, the effects of molding temperature and in-plane CTE of FR4 on warpage are studied, respectively. When molding temperature is 120 °C and in-plane CTE of FR4 decreases to 10.5 ppm/°C, the thermally induced warpage in the molding process is only about 0.31 mm, thus subsequent process of fan-out package can be conducted successfully.