Residual stress and thermally induced warpage are critical reliability concerns in power electronic packaging, particularly when employing sintered copper nanoparticle (Cu NP) interconnects. While these interconnects provide high thermal and electrical performance, they also introduce significant interfacial stresses during bonding that alter mechanical behavior during service. This study develops an integrated confocal Raman–analytical modeling framework to directly quantify and mechanistically interpret these stresses in a representative SiC/Sintered Cu NPs/Active Metal Brazing ceramic substrate (AMB) stack. Raman spectroscopy reveals a compressive interfacial stress field peaking at −334 MPa near the chip center with localized hotspots linked to microporosity. Complementary in-situ Moiré interferometry tracked warpage evolution during thermal cycle (30–310°C). Coupling this stress measurement with a three-dimensional thermoelastic model, and explicitly assigning the bonding temperature as the stress-free reference, enables accurate reproduction of the temperature-dependent warpage trajectory. The model predictions align with experimental interferometry within < 5% deviation. These results demonstrate that incorporating residual stress is essential to realistically capture thermo-mechanical evolution. The proposed Raman–model paradigm advances beyond prior purely numerical or purely experimental efforts by bridging quantitative stress mapping with predictive warpage modeling. This methodology provides essential insights for thermal-induced residual stress and warpage managements in high-temperature power electronics packaging, providing a stress-informed foundation for reliability assessment and design optimization.

Fan-Out Panel Level Package has become a trend in Silicon Carbide MOSFET packaging due to its superior electrothermal performance and cost-effectiveness. However, the increased size of multi-chip embedded FOPLP packaging introduces greater challenges in sample preparation and thermal-mechanical stresses. In this paper, a large-sized (20mm*20mm*0.78mm) FOPLP with 4 SiC MOSFETs embedded is investigated. A three-dimensional thermal-mechanical numerical model is derived based on heat conduction and elasticity theories. It utilized analytical solution of Fourier temperature conduction and finite difference results for thermoelastic models to describe the temperature and deformation distribution during the FOPLP operation. It also reveals the heat coupling issue of multiple chips. Compared with the finite element simulation, the proposed method shows less than 2.5 % error in temperature and 2.3 % error in deformation. The computational speed is one-tenth that of the finite element method, while the memory usage is reduced to one-fifth. To mitigate the influence of chip thermal coupling on temperature and warpage, an optimized layout was employed to achieve temperature uniformity improvement. Finally, FOPLPs with the two layouts were fabricated. The warpage was monitored using a digital image correlation platform. To achieve the same temperature, the current required for the optimized layout was increased by 9 %. The warpage of the optimized layout at 60 °C was reduced by 13.5 %, and at 100 °C it was reduced by 14.7 %, validating the accuracy of the model and the significance of thermal-decoupling.

Optical micro-electromechanical systems (MEMS) demand exceptional precision, yet warpage during the die attach process on printed circuit boards can compromise performance. Here, a three-dimensional thermoelastic analytical model has been developed based on Fourier heat conduction and supported beam theory. This model facilitates the in-situ calibration of solder parameters via confocal micro-Raman spectroscopy, ensuring that the simulated dynamic evolution of warpage during soldering aligns closely with digital image correlation experiments. The results show consistence with Finite Element Method with error less than 1 % and time saving more than 60 %. Orthogonal experimental analysis further reveals that substrate thickness and thermal expansion coefficient variations are the primary factors affecting warpage, while chip area has a negligible role. Given the practical challenges in reducing substrate thickness, a stress-balancing strategy incorporating an additional transition layer is proposed, which is effectively validated with a high-resolution three-dimensional profilometer. This work provides valuable insights into the predictive modeling and warpage behavior characterization, directly supporting improved mitigation strategies in the die attach process.

Silicon carbide (SiC) MOSFETs, as leading wide bandgap semiconductor devices, exhibit superior stability and reliability under high-temperature, high-switching frequencies, and high-power density operational conditions. SiC MOSFET with fan-out panel-level packaging (FOPLP) utilizes a redistribution layer (RDL) to substitute bonding wires, achieving low thermal resistance, electrical resistance, and parasitic inductance. This study proposes an optimal design strategy for SiC MOSFET FOPLP, considering parasitic inductance suppression, heat dissipation, thermal-mechanical reliability, and insulation enhancements. First, we establish the parasitic inductance, heat transfer network, and thermomechanical stress physical analytical models of SiC MOSFET FOPLP. Subsequently, the non-dominated sorting genetic algorithm (NSGA-II) and the improved multi-objective particle swarm optimization algorithm (MOPSO) are integrated to realize the co-optimization of parasitic inductance, thermal resistance, thermal stress, and electric field intensity distribution. Finally, we attain the optimal parameters of the SiC MOSFET FOPLP, i.e. chip thickness (x₁), solder thickness (x₂), RDL thickness (x₃), and chip side length (x₄) as 0.25 mm, 0.05 mm, 0.35 mm, and 6.00 mm, respectively. Additionally, according to comparison the MOPSO algorithm exhibits faster convergence and superior diversity than NAGA-II in the electrical-thermal-mechanical multiphysics co-optimization. Generally, the proposed physical analytical models combined with a multi-objective optimization method have a substantial guidance and forward-looking prospect on the design of SiC MOSFET FOPLP.

This study systematically investigated the potential of waste carbon fibers (WCFs) as a sustainable solution in enhancing the multiple induction heating healing of asphalt mixture, thereby tackling two major concerns: the environmental impact of WCFs and the durability of asphalt pavement. Firstly, four groups of asphalt binder samples with different WCFs contents were prepared. The viscosity and workability of WCFs modified asphalt binder were analyzed. Next, asphalt mixture containing 2% steel fibers was prepared at the optimal WCFs content, while control groups without WCFs were prepared with 2% and 4% steel fibers content. A comprehensive study was conducted on the induction heating rate, effective heating depth and surface temperature cooling rules of the asphalt mixture. Finally, by conducting multiple “fracture-healing” tests, the influence of WCFs on the healing efficiency of asphalt mixture was analyzed. The results revealed that WCFs increased the viscosity of the virgin asphalt, but excessive WCFs content hindered the workability. The optimal WCFs content was determined to be 1% (by weight of asphalt binder). WCFs enhanced the thermal conductivity of the asphalt mixture, accelerating heating and improving vertical heat transfer while reducing surface temperature decline. During multiple “fracture -healing” processes, the inclusion of WCFs enhanced the mechanical strength of the asphalt mixture, improved its healing efficiency, and increased the number of healings. Even after five cycles, the specimen with the most damage still showed a fracture energy recovery rate (FERR) of over 30%. In conclusion, WCFs significantly enhanced the multiple induction heating healing efficiency of the asphalt mixture.