This study investigates the size-dependent mechanical behavior and deformation mechanisms of sintered copper (Cu) nanoparticles (NPs) through micro-pillar (2–6 μm diameter) compression tests, scanning electron microscopy (SEM), transmission electron microscopy (TEM), transmission Kikuchi diffraction (TKD) analysis and molecular dynamics (MD) simulations. In-situ micro-pillar compression tests reveal a 25.9% reduction in yield strength (812 ± 64 MPa to 643 ± 47 MPa) with increasing pillar size, attributed to dislocation starvation in smaller pillars and porosity-driven strain localization in larger ones. TKD quantifies dynamic grain refinement (24.9% reduction in grain size) and geometrically necessary dislocation (GND) density escalation (74.8%), driven by stress gradients and grain boundary-mediated plasticity. Nanoindentation-derived elastic modulus (48.3 ± 11.1 GPa) exceeds micropillar values (29.5–33.9 GPa), reflecting substrate constraints in bulk testing. Microstructural analysis identifies a transition from shear banding in high-porosity pillars to uniform plasticity in denser systems, mediated by texture evolution (Brass/S components) and Schmid factor redistribution (62% increase in high-slip-activity grains). MD simulations of pressure-sintered Cu NPs elucidate atomic-scale mechanisms: dislocation nucleation at sintering necks, pore collapse-induced strain localization, and grain boundary sliding. These findings establish a multiscale framework linking porosity, grain refinement, and dislocation dynamics to mechanical performance, emphasizing microstructural optimization for enhanced reliability in microelectronic applications. The integration of MD simulations bridges atomic-scale mechanisms to microscale deformation, providing actionable insights for tailoring sintered Cu NPs via reduced porosity and controlled grain boundary architectures.

Silicon carbide (SiC) MOSFETs, as leading wide bandgap semiconductor devices, exhibit superior stability and reliability under high-temperature, high-switching frequencies, and high-power density operational conditions. SiC MOSFET with fan-out panel-level packaging (FOPLP) utilizes a redistribution layer (RDL) to substitute bonding wires, achieving low thermal resistance, electrical resistance, and parasitic inductance. This study proposes an optimal design strategy for SiC MOSFET FOPLP, considering parasitic inductance suppression, heat dissipation, thermal-mechanical reliability, and insulation enhancements. First, we establish the parasitic inductance, heat transfer network, and thermomechanical stress physical analytical models of SiC MOSFET FOPLP. Subsequently, the non-dominated sorting genetic algorithm (NSGA-II) and the improved multi-objective particle swarm optimization algorithm (MOPSO) are integrated to realize the co-optimization of parasitic inductance, thermal resistance, thermal stress, and electric field intensity distribution. Finally, we attain the optimal parameters of the SiC MOSFET FOPLP, i.e. chip thickness (x₁), solder thickness (x₂), RDL thickness (x₃), and chip side length (x₄) as 0.25 mm, 0.05 mm, 0.35 mm, and 6.00 mm, respectively. Additionally, according to comparison the MOPSO algorithm exhibits faster convergence and superior diversity than NAGA-II in the electrical-thermal-mechanical multiphysics co-optimization. Generally, the proposed physical analytical models combined with a multi-objective optimization method have a substantial guidance and forward-looking prospect on the design of SiC MOSFET FOPLP.

As the next generation of semiconductor devices, SiC MOSFETs have demonstrated significant performance improvements in switching loss, switching frequency, and high-temperature operation compared to Si-based MOSFETs. However, the long-term reliability of such devices and their packaging continues to be a major concern. Towards addressing this challenge, this study proposes a multi-objective optimization design method for parasitic inductance (L), thermal strain (?), and thermal resistance (R) of SiC MOSFETs with Fan-Out Panel-Level Packaging (FOPLP). First, the orthogonal experimental design was employed to investigate the thickness effects of baseplate, solder, die and redistribution layer (RDL) on L, e, and R. Then, the multi-objective optimization was developed to simultaneously reduce L, G, and R. Finally the fatigue lifetimes of the optimized and initial SiC MOSFET FOPLP structures were compared to verify the optimization's accuracy. Study findings include: (1) Solder thickness was the most significant influence factor for L, e and R of SiC MOSFET FOPLP, L and R increased, and e decreased with increasing solder thickness; (2) The proposed multi-objective optimization method coupled with a genetic algorithm achieved 14.79, 8.96, and 9.28% reduction of L, e, and R, respectively; (3) The fatigue lifetime of solder (SAC305) was evaluated using the Coffin-Manson model, with predicted lifetimes before and after optimization being 6786 and 7085 cycles, respectively, demonstrating that the proposed approach significantly enhanced the designed SiC MOSFET FOPLP's long-term thermal cycling reliability.