The degradation mechanisms of silicon carbide (SiC) VDMOSFET and trench metal oxide semiconductor field effect transistor (MOSFET) in a 60Co gamma irradiation environment were investigated. The degradation of electrical characteristics of SiC MOSFET in different working states after irradiation with different total ionizing doses (TIDs) was explored. The defects induced during the irradiation process were studied in annealing experiments conducted after irradiation. The reasons for the degradation of SiC MOSFET caused by TID were revealed, and a prediction model of threshold voltage (Vth) shift was proposed and verified through TCAD simulation. The Vth, breakdown voltage (BV), on-resistance R, input capacitance (Ciss), output capacitance Coss, and reverse transfer capacitance C _rss were measured at different irradiation doses and annealing conditions. Experimental results indicated that the degradation of both Ron and Ciss was primarily caused by the Vth shift. As the doses increased, the shift in Vth gradually reached saturation. Similar trends to VDMOSFET were observed in trench MOSFET but with greater sensitivity to TID. In addition, MOSFETs biased at zero voltage exhibited lower shifts in Vth compared with those under high gate bias conditions. Furthermore, the increase in defects in the gate oxide during irradiation and annealing processes were calculated. Finally, a model predicting Vth shift path was established, and its accuracy and limitations were determined. This study provides valuable insights into the effect of TID on SiC MOSFETs.

Pressureless sintered silver paste is widely used in SiC power electronic packaging for its superior thermal and electrical properties, enabling efficient heat dissipation and improved device reliability. Current thermal conductivity models frequently assume isotropic thermal behavior to simplify heat transfer calculations, yet these models neglect the inherent anisotropic porosity of sintered silver materials. This omission introduces errors in the characterization of these materials' thermal performance. This research investigates how the spatial anisotropic distribution of pressureless sintered silver's microstructure impacts QFN packaging's overall thermal conduction performance. This investigation is achieved by comparing lateral/vertical porosity differences between two materials and applying multidimensional thermal conductivity modeling. Two types of pressureless sintered silver were employed as die-attach materials to fabricate SiC MOSFET-based QFN packaging. The sintered microstructures' lateral and vertical cross-sections were characterized using scanning electron microscopy (SEM), enabling quantitative extraction of anisotropic porosity distributions. Subsequently, a numerical model was developed using the extracted porosity data to enhance the accuracy of heat transfer predictions in sintered silver layers while considering anisotropic thermal conductivity. Thermal resistance characterization was conducted on two QFN packages, and the accuracy of the proposed modeling methodology was validated by establishing the interrelation between experimental thermal resistance measurements and theoretical thermal conductivity predictions. This study demonstrates a refined approach to evaluating and optimizing sintered silver materials, providing a more accurate and application-driven thermal management strategy for SiC MOSFET power packaging.

In the domain of power electronics, especially for applications requiring high power, high temperature, and high frequency, Silicon Carbide Metal Oxide Semiconductor Field-Effect Transistors (SiC MOSFETs) stand out due to their excellent properties such as high thermal conductivity, elevated breakdown electric field, and minimal power loss. These devices are pivotal in the reliability and safety of electric vehicles, where avalanche-induced failures represent a significant risk within automotive uses. This study extensively explores the avalanche ruggedness of both planar and trench SiC MOSFET configurations through a combination of Unclamped Inductive Switching (UIS) testing in single and multiple pulse scenarios, and Technology Computer-Aided Design (TCAD) simulations. Initial UIS experiments revealed the primary failure mechanisms and their origins in SiC MOSFETs. Following empirical analysis, TCAD simulations were employed to develop comprehensive models of these devices., enhancing the understanding of failure dynamics during UIS conditions. The integration of empirical and simulation data supports the creation of advanced strategies to reduce the risk of avalanche failures, thereby enhancing the durability and reliability of Wide Bandgap Semiconductor devices.