With the ever increasing global energy consumption, modern power electronics need to be more energy efficient, have a smaller form factor and have better thermal performance. To achieve this goal, Wide-Bandgap (WBG) semiconductor materials, such as silicon carbide (SiC) and gallium nitride (GaN), are increasingly used instead of silicon (Si) in power applications such as electric vehicles and chargers. In particular GaN-based devices have a new breakthrough in the form of a vertically stacked GaN-Si cascode, which combines a normally-on GaN High-Electron-Mobility Transistor (HEMT) device with a normally-off Si Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) device stacked on top of the GaN HEMT device. Although the new configuration brought benefits to the table, it brought drawbacks to the thermal management of it: two heat sources stacked on top of each other. This causes both self-heating, but also coupled heating and combined with non-uniform heat dissipation across the device, the thermal behaviour becomes difficult to predict, which leads to suboptimal or over-engineered cooling solutions, reducing reliability and performance or increasing cost.

This thesis aimed to create insight and understanding of the heat dissipation and thermal behaviour inside a vertically stacked GaN-Si cascode. This was achieved by performing FEM simulations on the thermal behaviour in a vertically stacked GaN-Si cascode under different heat dissipation distributions, electrical characterisation of individual GaN HEMT and individual Si MOSFET dies to derive I-V and Ron characteristics, modelling of the heat dissipation and distribution using these electrical characteristics and thermal characterisation of a packaged vertically stacked GaN-Si cascode device using a Temperature-Sensitive Electrical Parameter (TSEP) and the Transient Dual Interface Method (TDIM) to derive Rthj-c under different operating conditions. It was found that the thermal performance was greatly influenced by the heat dissipation distribution and in turn the operating conditions (forward or reverse bias/conduction mode and how much current flows through the device). Based on these findings, recommendations were made to improve and extend the study on this topic, but also recommendations for future studies to improve packaging and cooling solutions.

Today’s cars are undergoing the greatest transformation the industry has seen. Power MOSFETs play a crucial role in making electronics more energy efficient by driving down switching losses and Rdson using a combination of next-generation trench technology and ultra-thin dies. Power MOSFET dies are becoming larger ( > 5 X 5 mm ) and thinner ( < 50 μm ) to meet the high performance lifetime requirements of the automotive industry. The high aspect ratio and the new chip designs with trench technology offer challenges for assembly, packaging and testing.

The majority of the research performed in the past, aimed to reduce the risk of die crack by improving equipment and process strategies in back-end semiconductor processing. This thesis study aims at improving die
strength from a front-end approach (device fabrication process) by making dies stronger to stress from die frontside. New chip designs are presented with new metal layer layouts for improved stress distribution. Materials like polyimide are investigated as new die top material for mechanical strengthening of die frontside. Key factors which influence die strength like trench-metal interaction, wafer stress and warpage are also analyzed in this thesis report.

In this study, ultra-thin power MOSFET dies are realised on 100 mm diameter silicon wafers with dimensions of 6 X 3 X 0.050 mm. These dies are mechanical equivalent in design, robustness to commercial trench power MOSFETs. The processed wafers are grinded from the backside to realise 50 μm thin wafers which are then sawned to obtain singulated dies. The strength of the dies are characterized by three-point bending tests and analyzed using probability plots for weibull distribution.