This study evaluates the reliability of die interconnect layers in a stacked die system fabricated using two different sintering agents: a microparticle-based silver paste and preform-based copper nanowires, intended for high-power packaging applications. Single-step sintering is performed to attach both dies at the same time, offering a faster and efficient assembly for improving scalability in manufacturing. The copper nanowires are sintered using KlettSintering method at 230° C for 5 minutes under a pressure of 20 MPa, while the silver paste was sintered pressure-free at 280 °C for 45 minutes in nitrogen. The assembled units were characterized using shear strength and microstructural analysis. Both sintering methods showed high porosity in the top die-attach layer compared to the bottom die-attach layer, which is reflected in lower shear values for top die (35 MPa) compared to bottom die (45 MPa) in the silver sintered unit. The long-term reliability of the die-stack systems was assessed through a 500 -hour high-temperature storage test and a 500-cycle temperature cycling test, revealing significant impacts of thermo-mechanical stresses on die attach layers of both sintered units. The KlettSintered system maintained consistent performance throughout the reliability tests but exhibited coarsening and oxidation during temperature cycling. Furthermore, the study identifies areas for potential improvement, particularly in improving multi-die sintering performance in a single-step process, which is crucial for ensuring durability in high-power applications.

Power MOSFET dies in the automotive industry are becoming larger (>5 × 5 mm) and thinner (<50 µm) to meet high-performance and lifetime requirements. Ensuring the mechanical robustness of these large ultrathin chips is crucial for reliable electronic devices and high-throughput packaging processes. The high aspect ratio and advanced chip designs incorporating trench technology present significant challenges in semiconductor assembly, packaging, and testing. This paper introduces an experimental front-end strategy aimed at strengthening the front side (FS) of large ultrathin dies using various die-top systems. Industry-equivalent 50 µm thick dummy power MOSFET dies were fabricated to evaluate the efficacy of different chip designs and materials, such as polyimide (PI), in mitigating fracture risks. Fabrication-induced stresses and warpage in the device layers were measured using a thin-film stress measurement tool. Additionally, the FS strength of the ultrathin dies was assessed using the three-point bending method, with the resulting data analyzed via two-parameter Weibull distribution plots. Results demonstrated that the deposition of 5 µm PI on the nitride die topside significantly increased die strength from 339 MPa to 760 MPa, with 5 µm PI proving more effective for die strengthening than 10 µm. The interaction between the metal-trench layer and the die was found to be critical to the robustness of ultrathin dies, influenced by the pattern and layout of the trenches. Die-top metallization designs, such as meandering patterns, showed promising improvements in die strength compared to standard designs. A proposed chip layout aims to maximize PI coverage for clip-bonded products on the die topside, leveraging its strengthening effect. The study also demonstrated that dummy reference chips can facilitate rapid and straightforward evaluation of extensive design experiments to identify robust chip designs.