Modeling and monitoring advanced power semi-conductor packages are challenging due to their multiphysics behavior, structural complexity, and the high computational cost associated with detailed models. Conventional high-fidelity approaches, such as finite element models, provide high accuracy but are often unsuitable for applications like health monitoring, while purely data-driven models may lack physical interpretability and robustness under degradation.This paper proposes the concept of a multi-agent digital twin framework to address these challenges by decomposing the overall system into interconnected virtual domains with different roles and fidelity levels. The approach is demonstrated for health monitoring of a SiC MOSFET in a DC-DC buck converter. A three-agent architecture is implemented, consisting of a temporal ANN for system identification, a decision layer for failure detection and localization, and a parametric reduced-order thermal model for failure assessment. Experimental results show that the proposed framework can accurately identify system behavior, detect and localize failures, and quantify parameter variations associated with degradation.

Due to the better performance of the Wide Band Gap (WBG) devices, there has been a paradigm shift toward WBG-based power modules for diverse applications like Electric Vehicles (EVs). However, the high parasitic inductance value of power modules hinders these devices from unlocking their full potential. Therefore, this paper comprehensively reviews SiC-based Single Side Cooling (SSC) power modules that benefit from low parasitic inductance. The paper also discusses the need to develop newer power modules using modern packaging methods. The surveyed power modules are categorized into three main groups, namely wire bonding, hybrid, and 3D packaging methods. This classification contains several vital parameters of the studied power modules, such as nominal and Double Pulse Tests (DPT) power ratings, parasitic inductance, size, etc. The main features and characteristics corresponding to the reviewed power modules' packaging methods and techniques are also briefly described. Finally, a thorough discussion about challenges and future trends is highlighted before concluding the paper.

The paper presents a degradation for remaining useful lifetime framework for smart power stages (SPS) with an integrated temperature sensor for electronic control units (ECU). A reduced order state space model with physically meaningful time constants is derived from finite element simulations. The state space model is the core of the damage estimation of the SPS during operation. A framework for remaining useful lifetime estimation is presented simulating degradation based on an estimated mission profile for cars. Temperature cycles are extracted and used to estimate the time constant drift representing package degradation. An exemplary approach on how to integrate degradation monitoring into a lifetime approximation of the package is presented. The state space model is extended for estimator based predictions to integrate the model in future test benches for real life monitoring and remaining useful life predictions of active devices.

This study evaluates the reliability of die interconnect layers in a stacked die system fabricated using two different sintering agents: a microparticle-based silver paste and preform-based copper nanowires, intended for high-power packaging applications. Single-step sintering is performed to attach both dies at the same time, offering a faster and efficient assembly for improving scalability in manufacturing. The copper nanowires are sintered using KlettSintering method at 230° C for 5 minutes under a pressure of 20 MPa, while the silver paste was sintered pressure-free at 280 °C for 45 minutes in nitrogen. The assembled units were characterized using shear strength and microstructural analysis. Both sintering methods showed high porosity in the top die-attach layer compared to the bottom die-attach layer, which is reflected in lower shear values for top die (35 MPa) compared to bottom die (45 MPa) in the silver sintered unit. The long-term reliability of the die-stack systems was assessed through a 500 -hour high-temperature storage test and a 500-cycle temperature cycling test, revealing significant impacts of thermo-mechanical stresses on die attach layers of both sintered units. The KlettSintered system maintained consistent performance throughout the reliability tests but exhibited coarsening and oxidation during temperature cycling. Furthermore, the study identifies areas for potential improvement, particularly in improving multi-die sintering performance in a single-step process, which is crucial for ensuring durability in high-power applications.

This study investigates the interface strength and fracture behavior of sintered copper (Cu) nanoparticles (NPs) for all-Cu integration in advanced microelectronics packaging. Micro-cantilever bending tests on three configurations (Cu NP-notched, interface-notched and un-notched micro-cantilevers) were analyzed using scanning electron microscopy (SEM), transmission electron microscopy (TEM), transmission Kikuchi diffraction (TKD) and cohesive zone model (CZM). The interface-notched micro-cantilevers demonstrate superior fracture resistance, with a stress intensity factor (K_Q) of 2.88±0.10 MPa m^1/2, compared to 2.12±0.11 MPa m^1/2 for Cu NP-notched micro-cantilevers. Simulation results, consistent with experimental results, reveal that Cu NP-notched micro-cantilevers exhibit lower fracture resistance due to porosity and stress concentrations, while interface-notched micro-cantilevers show enhanced strength, attributed to robust bonding and reduced void distribution. Un-notched micro-cantilevers display superior load-bearing capacity, with cracks bypassing the interface and propagating through porous regions. Moreover, in un-notched micro-cantilevers, a synergistic deformation mechanism is observed, where crack propagation through the sintered Cu NPs coexists with plastic slip deformation in the Cu substrate. These findings highlight the strong interfacial bonding and effective stress transfer at the Cu substrate-sintered Cu NP interface, validating the feasibility of direct sintering using Cu NPs without additional coatings.

In this study, we introduced a hybrid Potts-phase field model to simulate the co-evolution of grain growth and pores migration in sintered silver layers. The Potts model is good at capture the grain growth dynamics, while the phase field model describes the evolution of the porous network. These models are coupled via a hybrid free energy function to achieve a realistic representation of the microstructure evolution. This study further extends the hybrid model by incorporating (a) a flexible exchange interaction matrix to model the crystal anisotropy in grain growth, (b) Glauber or Kawasaki dynamics to describe different diffusion mechanisms, and (c) the effect of pinning sites, representing impurity-driven grain boundary stabilization. The computational framework is implemented using Taichi Lang, which allows for efficient parallel simulations. Results show that the model effectively captures the long-term evolution of the sintered silver microstructure in good agreement with experimental observations. This hybrid model is a powerful tool to predict microstructural reliability of sintered silver die attach layers, supporting material design and process optimization for high-power electronic applications.

Sintered Cu nanoparticles (NPs) are promising for high-performance electronics due to their excellent thermal and electrical conductivity, as well as mechanical reliability. This study investigates the microscale mechanical behavior of sintered Cu NPs with a bimodal particle size distribution, focusing on strain rate and temperature effects. Micro-pillar compression tests were performed across strain rates of 0.0001 s⁻¹ to 0.01 s⁻¹ and temperatures from 25 °C to 350 °C. Results show that higher strain rates enhance yield strength through strain-rate hardening, while elevated temperatures lead to thermal softening and reduced mechanical stability. The Anand viscoplastic model accurately predicts these deformation behaviors. Microstructural analysis via scanning electron microscopy (SEM) and transmission electron microscopy (TEM) reveals localized deformation at 175 °C, with dislocations concentrated near the top surface and persistent porosity below, whereas at 350 °C, re-sintering and grain boundary diffusion create a denser microstructure. Phase-field fracture modeling further elucidates crack propagation, emphasizing the role of pore size and temperature. This combined experimental and modeling approach enhances understanding of viscoplastic deformation and fracture mechanisms in sintered Cu NPs, informing their use in interconnects, power electronics and thermal management systems.

The mechanical strength of sintered nanoparticles (NPs) limits their application in advanced electronics packaging. In this study, we explore the anisotropy in the microstructure and mechanical properties of sintered copper (Cu) NPs by combining experimental techniques with molecular dynamics (MD) simulations. We establish a clear relationship between processing conditions, microstructural evolution, and resulting properties in pressure-assisted sintering of Cu NPs. Our findings reveal that pressure-assisted sintering induces significant anisotropy in the microstructure, as evidenced by variations in areal relative density and the orientation distribution of necks formed during sintering. Specifically, along the direction of applied pressure, the microstructure exhibits reduced variation in areal relative density and a higher prevalence of necks with favorable orientations. The resulting anisotropic mechanical properties, with significantly higher strength along the pressure direction compared to other directions, are demonstrated through micro-cantilever bending tests and tensile simulations. This anisotropy is further explained by the combined effects of strain localization (influenced by areal relative density) and the failure modes of necks (determined by their orientation relative to the loading direction). This work provides valuable insights into the analysis of sintered NPs microstructures and offers guidance for optimizing the sintering process.

This study investigates the microstructure evolution and mechanical behavior of bimodal-sized sintered copper (Cu) nanoparticles (NPs) under varying sintering pressures. Micro-pillar compression tests reveal a transition from collapse-dominated to compaction-driven deformation as sintering pressure increases. Transmission electron microscopy (TEM) and transmission Kikuchi diffraction (TKD) analyses identify a two-stage deformation mechanism—initial pore compaction followed by intragranular slip—fundamentally distinct from bulk Cu. Molecular dynamics (MD) simulations further reveal that large particles promote dislocation-mediated plasticity by accommodating intragranular slip, while small particles enhance load transfer through localized shear-compaction, together enabling uniform strain distribution and supporting the experimentally observed strain accommodation. The resulting microstructure achieves a combination of high yield strength (up to 320 MPa) and low elastic modulus (20 GPa), offering a compliant yet robust response. These findings elucidate a unique processing–structure–property relationship and provide a rational basis for designing porous metal interconnects capable of withstanding thermomechanical stresses in advanced electronic packaging.

Silicon-Carbide (SiC) MOSFETs are widely used in high-power and high-efficiency applications such as electric vehicles and power supplies. However, long-term reliability remains a critical concern, particularly under extreme operating conditions. This work aims to explain the health monitoring of SiC metal oxide-semiconductor field effect transistors (MOSFETs) through precise junction temperature (T_j) profiling based on performed measurements. The study focuses on the temperature-dependent behavior of the on-resistance (RDS(on)), a key parameter that varies with the aging, degradation, and temperature of the device. By systematically measuring R_DS(on) at different temperatures and at various stages of the operating life of the device, we can establish a predictive model to assess the health of SiC MOSFETs. The importance of pulse duration of the drain current is stressed to avoid the self-heating effect with some device physics insights. The proposed methodology enables better understanding of the SiC MOSFET performance for future real-time condition monitoring, facilitating early failure detection and lifetime estimation. This approach provides valuable information for improving reliability and optimizing maintenance strategies in power electronics systems. Experimental results validate the effectiveness of the proposed method and give direction for future research opportunities.

The introduction of silicon carbide(SiC) has reduced the superiority of traditional silicon-based power module pack-aging strategies. As packaging strategies become increasingly complex, classical thermal modelling tools often prove inadequate in balancing efficiency with accuracy. Integrating these tools with machine learning (ML) can significantly enhance their application potential. This discussion commences by addressing the pressing issues in thermal modelling of SiC modules, specifically the challenges associated with multiple heat sources and heat spreading. During the design stage, ML models can swiftly simulate the thermal response of various packaging strategies, aiding engineers in eliminating ineffective options. In the monitoring phase, the employment of a digital twin enables a deeper investigation into degradation phenomena. This article reviews the current status and explores the potential applications of ML in thermal modelling of SiC power modules.

This article introduces an online condition monitoring strategy that utilizes a transient heat pulse to detect package thermal performance degradation. The metric employed is the temperature-dependent transient thermal impedance "Zth(t, Tamb)."The proposed methodology offers quantitative insights into package thermal performance degradation and effectively pinpoints the presence of multiple failure mechanisms. A thermal test chip assembled in a power quad flat no-lead package is used in this study to demonstrate the methodology. The packaged devices are first characterized to determine the transient pulse duration, a critical parameter to monitor a specific region of interest. Subsequently, package thermal performance degradation is continuously monitored online during thermomechanical cycling lifetime experiments. The validity of the measurement results is later confirmed through acoustic imaging and cross-sectional analysis. The changes observed in Zth(t, Tamb) over thermal cycling correspond to the delamination of the active metal layers on the die and cohesive failure on the die attach. This article further includes a comparative summary, highlighting the distinctions between the proposed and industry-standard test methods. In conclusion, the importance of online condition monitoring to detect early signs of failure is emphasized, and the proposed methodology s practical applicability in real-life scenarios is briefly discussed.

Power MOSFET dies in the automotive industry are becoming larger (>5 × 5 mm) and thinner (<50 µm) to meet high-performance and lifetime requirements. Ensuring the mechanical robustness of these large ultrathin chips is crucial for reliable electronic devices and high-throughput packaging processes. The high aspect ratio and advanced chip designs incorporating trench technology present significant challenges in semiconductor assembly, packaging, and testing. This paper introduces an experimental front-end strategy aimed at strengthening the front side (FS) of large ultrathin dies using various die-top systems. Industry-equivalent 50 µm thick dummy power MOSFET dies were fabricated to evaluate the efficacy of different chip designs and materials, such as polyimide (PI), in mitigating fracture risks. Fabrication-induced stresses and warpage in the device layers were measured using a thin-film stress measurement tool. Additionally, the FS strength of the ultrathin dies was assessed using the three-point bending method, with the resulting data analyzed via two-parameter Weibull distribution plots. Results demonstrated that the deposition of 5 µm PI on the nitride die topside significantly increased die strength from 339 MPa to 760 MPa, with 5 µm PI proving more effective for die strengthening than 10 µm. The interaction between the metal-trench layer and the die was found to be critical to the robustness of ultrathin dies, influenced by the pattern and layout of the trenches. Die-top metallization designs, such as meandering patterns, showed promising improvements in die strength compared to standard designs. A proposed chip layout aims to maximize PI coverage for clip-bonded products on the die topside, leveraging its strengthening effect. The study also demonstrated that dummy reference chips can facilitate rapid and straightforward evaluation of extensive design experiments to identify robust chip designs.

Resin-reinforced Ag sintering materials represent a promising solution for die-attach applications in high-power devices requiring enhanced reliability and heat dissipation. However, the presence of resin and intricate microstructure poses challenges to its thermal performance, and improvement strategies remain unclear. This work utilizes 3D FIB-SEM nanotomography to reconstruct the microstructure of this material under various process conditions. The analysis reveals that, even with an Ag volume fraction as low as 47.3%, Ag particles form a robust 3D network. Geometric tortuosity quantifies the effect of different sintering conditions on the Ag particle network in all spatial directions. Effective thermal conductivity is simulated based on realistic microstructure models. Results show a significant negative correlation between tortuosity and effective thermal conductivity. Increasing sintering temperature in Model B notably reduces tortuosity and enhances effective thermal conductivity. Sensitivity analysis underscores the dominant role of Ag volume fraction in regulating effective thermal conductivity. Finally, transient thermal impedance measurement of this material as a thin die-attach layer in actual high-power devices demonstrated its application potential. This article strives to explore the relationship between process, microstructure, and thermal properties of this material to provide a reference for further development.

Prognostic monitoring of power quad flat no-lead (PQFN) packages with four distinct silver pastes, each varying in material composition (pure-Ag and resin-reinforced hybridAg) and sintering processes (pressure-assisted and pressureless), was investigated in this study. The PQFN packages with silver sintered die-attach materials were subjected to thermal cycling tests (?55 ° C to 150 ° C), and the performance degradation was evaluated based on the following metrics: 1) electrical ON-state resistance RDSon monitored periodically at specific thermal cycling intervals and 2) transient thermal impedance Zth(t = 0.1 s) monitored online during thermal cycling. These measurements were further validated using acoustic microscopy imaging and cross-sectional inspection. The pressureless Ag-sintering material demonstrated comparable performance to pressure-assisted Agsintering, with a dense microstructure, and consistent electrical and stable thermal performance. Whereas the pressureless resinreinforced hybrid-Ag material exhibited degradation with a relative increase of 33% in RDSon, 38% in Zth(t = 0.1 s), and 67% delamination of the die-attach interface over 1000 cycles. These findings suggest that pressureless Ag-sintering may offer a viable alternative to pressure-assisted methods for lead (Pb)- free die-attachments, while resin-reinforced hybrid-Ag requires further development for improved thermomechanical reliability..

The increasing awareness of environmental concerns and sustainability underlines the importance of energy-efficient systems, renewable energy technologies, electric vehicles, and smart grids. Hence, stringent constraints and safety regulations have been prompted to meet reliability standards in power electronics. This chapter provides a comprehensive outlook on the current state of power semiconductor devices, field-critical applications, dominant degradation mechanism (chip-related and package-related), and the emerging measurement techniques for reliability/condition monitoring. This chapter delves into the underlying physics behind each reliability measurement method reviewed. A comparative summary of cost, complexity, online monitoring capability, accuracy, and intrusiveness is provided to enable readers to make informed decisions about the measurement methods. This chapter emphasizes the significance of early fault detection through online monitoring, as it can effectively reduce system downtime for seamless non-interruptive operation.