This paper introduces a novel control strategy for Modular Multilevel Resonant converters (MMR) in Solid-State Transformer (SST) applications, with a focus on medium-voltage conversion for hydrogen electrolyzers. The article first reviews voltage control methods in MMR, analyzing their operational principles and regulation capabilities. A continuous modulation index control method with double-step staircase waveform modulation is then proposed, simplifying the control scheme to a single control variable while maintaining robust controllability. Meanwhile, the proposed approach maintains comparable power loss and harmonic performance to existing methods under the investigated operating conditions. Simulations and experiments are conducted to verify the feasibility and practical implementation of the proposed approach.

This work proposes a nondestructive framework to track the time- and depth-resolved evolution of oxide traps in 4H-SiC metal-oxide-semiconductor (MOS) structures during time-dependent dielectric breakdown (TDDB) stress. The approach combines time-resolved gate admittance measurements with a distributed oxide admittance model and frequency-temperature depth mapping to reconstruct the measured dispersion at flatband voltage and recover nonuniform oxide trap profiles without imposing an a priori spatial distribution. Applied to long duration negative-bias TDDB, the extracted profiles reveal a strongly depth-nonuniform and field-accelerated defect build-up: higher stress not only increases the trap population, but also broadens the active defect region deeper into the oxide as breakdown is approached. By tracking the average trap density and the centroid of oxide trapped charge in the probed oxide region, we quantify the spatial evolution and relate it to the concurrent transients in gate leakage current, flatband voltage shift, and increment of interface trap density, without relying on destructive techniques, such as transmission electron microscopy, thus preserving the device for continuous evaluation. The same methodology is further demonstrated on stressed silicon carbide (SiC) power mosfets, supporting device-level relevance and providing a workflow for depth-resolved characterisation of SiC gate oxide degradation under negative stress.

Failures associated with thermo-mechanical fatigue are one of the dominant reasons for faults in power electronic converter-based electrical systems. This review explores such thermal stress-induced reliability challenges in power converters, focusing on key package-related failure mechanisms such as bond-wire fatigue, solder degradation, and chip metallization wear-out. The study emphasizes the importance of mission-profile-based reliability assessment, highlighting the effects of operational and environmental conditions on the long-term performance of power modules. Key findings reveal how repetitive thermal cycling and environmental variations lead to critical failures, underscoring the need for effective thermal management and design-for-reliability strategies. The primary goal of this paper is the quantitative, comparative reliability analysis across multiple high-power applications, moving beyond qualitative summaries. This review aims to support future research on predictive reliability modeling, mission-profile-based lifetime estimation, and robust design strategies for wide-bandgap-based high-power converters. Ultimately, the insights provided are intended to guide the development of more robust power electronic systems for emerging energy and mobility infrastructures.

Higher switching speeds and power densities enabled by SiC MOSFETs make accurate, time-resolved junction-Temperature (Tj) estimation under realistic switching conditions increasingly important for performance validation, thermal design, and reliability assessment. This work presents an electro-Thermal co-simulation framework for SiC MOSFET double-pulse testing, combining measured switching waveforms with a compact thermal network (Cauer model) to translate transient switching-loss energy into (Tj) evolution. A Peak-Power-Threshold (PPT) method is introduced to robustly identify the switching interval and compute instantaneous power and switching energies (Eon, Eoff) from experimental data, enabling consistent comparison between measurement and simulation across few operating points. The proposed approach links dynamic loss extraction to junction-Temperature estimation in a unified workflow, supporting more reliable interpretation of double-pulse tests and improving confidence in electro-Thermal estimation for high-performance SiC power converters.

This paper presents the design and control of 12 kW medium voltage Modular Multilevel Converter (MMC) prototype, providing a general overview on both the component and system levels. A top level functional overview of the sub-module (SM) converter design including features like semiconductor temperature monitoring and protections for over-voltage, overcurrent, and over-temperature to enhance reliability. The paper also offers a comprehensive system overview, utilizing OPALRT as a high-level controller. To demonstrate the effectiveness of the proposed design, a 12-kW, three-phase MMC prototype was constructed, consisting of four full-bridge (FB) SMs in each converter arm. The paper explains communication management and the integration of analog and digital signals between the physical system and the user interface controller. Finally, the system's output under various operating conditions is analyzed and presented.

Modular multilevel converters (MMCs) are widely used in various applications due to their scalability, efficiency, and fault-tolerant capabilities. This article proposes a fault-tolerant methodology tailored for full-bridge (FB) submodules (SMs) in MMCs to enhance system reliability under open-circuit faults (OCFs) in insulated-gate bipolar transistors (IGBTs). The method adopts a hybrid approach, using control logic adjustments to reconfigure faulty SMs into half-bridge (HB) configuration for T2/T3 faults while employing redundant SMs for T1/T4 faults. Accurate fault detection and localization are achieved through established methods, such as state observers and voltage comparisons. It is shown using MCS that the proposed method can improve the 17 kV 10 MVA converter reliability by almost 25% over solely redundancy-based solution for given lifetime requirements. Finally, using a lab-scale FB MMC prototype, it is experimentally shown that the proposed reconfiguration technique can successfully localize the fault and revert to normal operating requirements by shifting from FB to HB SM configuration in approximately 20 ms of fault initiation.

Targeting a climate-neutral maritime sector drives the adoption of the all-electric ship (AES). While AESs can utilize both ac and dc shipboard power systems (SPS), a dc system offers advantages in efficiency, power density, and source synchronization. However, the enhanced network complexity of dc grids combined with the high penetration of power electronic devices and harsh environmental conditions can compromise the system's reliability. Therefore, this article provides an overview of the reliability aspect of dc-SPSs, addressing the power system design, adequacy assessment, and reliability improvement. First, the performance tradeoffs associated with the SPS design are examined, revealing how changes in the power system topology and dc bus structure impact the vessel's reliability along with other performance parameters. Second, a hierarchical reliability model framework is proposed for the adequacy assessment of dc-SPSs, considering the reliability from the component level up to the system level. To determine the system-level reliability, multiple probabilistic methods, including simulation and analytical models, are compared using a propulsion subsystem example. Finally, an overview of the reliability improvement strategies is provided, addressing methods at the system, device, and component level. These three topics combined aim to provide guidance in the design of future reliable dc-SPSs.

This study investigates the techno-economic impacts of various pricing policies on a photovoltaic (PV) system combined with battery energy storage (BES) as a single integrated system within a Dutch residential building. With the increasing adoption of PV systems, managing reverse power flow and grid stability becomes crucial. The study evaluates different scenarios, including net metering, feed-in tariffs (FiT) with time-of-use (TOU), RTP pricing, and subsidised BES. Using a multi-objective genetic algorithm, the optimal size and charging/discharging patterns of the PV-BES system were determined. The optimisation simultaneously minimises the Net Present Cost (NPC) and maximises the Self-Consumption Rate (SCR), to determine the PV-BES size that achieves an optimal balance between economic and technical performance. Results indicate that RTP pricing significantly enhances SCR. While the levelised cost of electricity (LCOE) and payback periods (PBP) are initially higher in the RTP pricing scenario, subsidising BES can mitigate these disadvantages. Additionally, incorporating price limit control variables into the energy management system (EMS) optimises the charging/discharging cycles, extending BES lifetimes and potentially increasing future revenues. These findings provide insights for policymakers to balance economic benefits and grid technical requirements through effective PV-BES integration.

Modular Multilevel Converters (MMCs) offer significant advantages in the medium to high-voltage settings. The modular architecture of MMCs allows for redundant submodules (SMs) to improve overall reliability. These redundant SMs can be deployed using various redundancy strategies, such as Load-Sharing Active Redundancy Strategy (LS-ARS), Fixed-Level Active Redundancy Strategy (FL-ARS), and Standby Redundancy Strategy (SRS). The primary contribution of this paper is the introduction of guidelines for applying Monte Carlo Simulation (MCS) and a comprehensive methodology for its application across various redundancy strategies. This enables precise planning of preventive maintenance and estimation of the number of faulty SMs with a specific lifespan in the MMC. More importantly, MCS is applied to estimate the reliability of the MMC applying Mission Profile for SRS and LS-ARS where analytical solutions are unavailable. An analysis of uncertainty and the applicability of MCS is also presented to demonstrate the advantages of MCS over analytical methods. The computational time required for applying MCS across different redundancy strategies and arm levels is also assessed.

Properly addressing uncertainties in reliability analysis is essential for realistic lifetime predictions of power devices. This paper investigates parameter uncertainties on the lifetime estimation of power devices using an empirical lifetime model and Monte Carlo simulations. Key parameters such as junction temperature swings (ΔT _j), minimum junction temperature (T _{j, min}), and lifetime model constants are analyzed for their impacts on lifetime outcomes. Sensitivity analysis reveals significant effects from variations in parameters like β ₁ and ΔT _j on the expected lifetime and its variability. Simultaneous variations across all parameters further highlight the dominant influence of β ₁ on lifetime predictions. The analysis suggests that a 5 % uncertainty margin appears to offer a balanced trade-off between realistic lifetime estimations and predictability. This Study underscores the importance of considering parameter uncertainties for precise reliability evaluations. It addresses a critical gap by examining the rationale behind commonly assumed 5 %, and 10 % uncertainty margins in lifetime modeling. By systematically evaluating these margins’ impacts on key reliability parameters, the study provides a framework for selecting reasonable assumptions based on physical insights and variability analysis, advancing the reliability modeling of power devices.

Silicon-Carbide (SiC) MOSFETs are widely used in high-power and high-efficiency applications such as electric vehicles and power supplies. However, long-term reliability remains a critical concern, particularly under extreme operating conditions. This work aims to explain the health monitoring of SiC metal oxide-semiconductor field effect transistors (MOSFETs) through precise junction temperature (T_j) profiling based on performed measurements. The study focuses on the temperature-dependent behavior of the on-resistance (RDS(on)), a key parameter that varies with the aging, degradation, and temperature of the device. By systematically measuring R_DS(on) at different temperatures and at various stages of the operating life of the device, we can establish a predictive model to assess the health of SiC MOSFETs. The importance of pulse duration of the drain current is stressed to avoid the self-heating effect with some device physics insights. The proposed methodology enables better understanding of the SiC MOSFET performance for future real-time condition monitoring, facilitating early failure detection and lifetime estimation. This approach provides valuable information for improving reliability and optimizing maintenance strategies in power electronics systems. Experimental results validate the effectiveness of the proposed method and give direction for future research opportunities.

High-power flexible dc links employ modular multilevel converters (MMC) for compact active power redirection in medium and high voltage grids. During contingencies, such converters may need to provide an enhanced active power capacity to avoid overload in vulnerable grid locations. This paper achieves this target by using the capacitor voltage ripple margin of the MMC submodules (SM) to enhance the dc voltage beyond the rated value. This voltage enhancement enables the enhanced active power capacity of the MMC while maintaining rated electro-thermal stresses on the components. Moreover, dynamically varying the dc side voltage reduces the MMC's circulating current, improving its operating efficiency. Because the average capacitor voltage is controlled to remain constant, the overall stresses and harmonic performance of the enhanced MMC remain the same as in the base case. In this paper, the analytical expressions for the voltage and power enhancement limits are derived, revealing a dependence on the grid-injected reactive power. Furthermore, a controller is designed to achieve stable operation during transient conditions when the power enhancement is carried out. Finally, the enhancement concept is validated using simulations and experiments with a down-scaled laboratory MMC prototype.

In DC shipboard power systems (DC-SPS), the enhanced network complexity and high penetration of power electronic devices make the system level reliability a critical design aspect. This paper proposes a stochastic framework for the reliability assessment of DC-SPSs based on a three-stage Monte Carlo (MC) simulation, including component failure sampling, active fault propagation, and reliability index calculation. The proposed MC framework is verified for a simplified meshed DC grid through comparison with an analytical method. Later, the advantages of the MC method are demonstrated for a dynamic positioning vessel equipped with a ring-type DC power system architecture. The results quantify the impact of redundancy on the reliability of a DC-SPS, show the spread in the subsystem repair times, and reveal the system's availability during both the initialization and steady-state. Combined, the simulation results reveal the strengths and weaknesses of the designed grid, guiding the focus for future reliability enhancements.

Modular multilevel converters are favorable for efficiently operating high-power usages. The required number of components significantly increases when higher modularity is introduced for the given voltage level, thus reducing the system's reliability. This article suggests a mixed redundancy strategy (MRS) that combines the operational concepts using active and spare redundant submodules. It is shown that more than 50% higher B10 lifetime (the point in time when the system has a 90% probability of survival) is achievable as compared to reliability improvement using fixed-level active redundancy strategy, load-sharing active redundancy strategy, and standby redundancy strategy with the same number of redundant submodules. The tradeoff between operational efficiency and investment cost is explored to define the boundary for selecting the MRS over other redundancy strategies with varying dc-link voltages and average converter loading, considering a ten-year payback period and equivalent B10 lifetime. The change in viability boundary for the MRS is established with increasing B10 lifetime and its sensitivity to power electronic component costs and assumed failure rate. The effect of power capacity with a higher switch current rating is evaluated. Also, the Monte Carlo simulation methodology is proposed to evaluate the practicality and effectiveness of the proposed MRS scheme. Finally, the insights of this study are applied to existing literature.

The Dual Active Bridge (DAB) is a popular DC-DC converter for bidirectional power transfer in applications such as the re-emerging technology of flow batteries. For such applications, it is essential to design the DAB for the wide voltage range operation of batteries, specifically focusing on its non-linear characteristics. The existing design methods utilise an optimisation algorithm to minimise the losses of the DAB at various equidistant voltage points in the voltage range. The resulting design is less efficient as it gives too much weight to insignificant operating points. This article proposes a new method that uses the flow battery characteristics to determine the operating points at which minimisation should be performed. The proposed method is validated with simulation results.

The rising demand for electric vehicles (EVs) in the face of limited grid capacity encourages the development and implementation of smart charging (SC) algorithms. Experimental validation plays a pivotal role in advancing this field. This article formulates a hierarchical mixed integer programming EV SC algorithm designed for low voltage (LV) distribution grid applications. A flexible receding horizon scheme is introduced in response to system uncertainties. It also considers the practical constraints in protocols, such as IEC/ISO 15118 and IEC 61851-1. The proposed algorithm is verified and assessed in a power hardware-in-the-loop testbed that incorporates models of real LV distribution grids. Furthermore, the algorithm's capabilities are examined through eight scenarios, out of which four focus on the uncertainties of the input data and two address the engagement of extra grid capacity restrictions. The results demonstrate that the SC algorithm adequately lowers the EV charging cost while fulfilling the charging demand, and substantially reduces the peak power as well as the overloading duration, even when faced with input data uncertainty. The additional grid restrictions in place are proven to improve peak demand reduction and overloading mitigation further. Finally, the limitations and potentials of the developed algorithm are scrutinized.