Temperature dependent trap characterisation and modelling of silicon carbide MOS capacitor
J. Li (TU Delft - Electronic Components, Technology and Materials)
S. Vollebregt (TU Delft - Electronic Components, Technology and Materials)
Y. Zhang (TU Delft - Electronic Components, Technology and Materials)
A. Shekhar (TU Delft - DC systems, Energy conversion & Storage)
Alexander May (Fraunhofer Institute for Integrated Systems and Devices Technology IISB)
Willem van Driel (TU Delft - Electronic Components, Technology and Materials)
G. Zhang (TU Delft - Electronic Components, Technology and Materials)
More Info
expand_more
Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons.
Abstract
Due to the deficient passivation of the interface between silicon carbide and silicon dioxide, the defect-induced capture and release of trapped charges triggered by external Bias Temperature Stress (BTS) leads to parameter shifts and degraded device performance. This study models the trap-induced transient current in silicon carbide metal-oxide-semiconductor capacitors, providing insight into how capacitance and conductance change during C-V measurements under conditions of high temperature, varied frequency, and varied applied voltage.