Temperature dependent trap characterisation and modelling of silicon carbide MOS capacitor
Jinglin Li (TU Delft - Electrical Engineering, Mathematics and Computer Science)
Sten Vollebregt (TU Delft - Electrical Engineering, Mathematics and Computer Science)
Yaqian Zhang (TU Delft - Electrical Engineering, Mathematics and Computer Science)
Aditya Shekhar (TU Delft - Electrical Engineering, Mathematics and Computer Science)
Alexander May (Fraunhofer Institute for Integrated Systems and Devices Technology IISB)
Willem D. van Driel (TU Delft - Electrical Engineering, Mathematics and Computer Science)
Guoqi Zhang (TU Delft - Electrical Engineering, Mathematics and Computer Science)
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Abstract
Due to the deficient passivation of the interface between silicon carbide and silicon dioxide, the defect-induced capture and release of trapped charges triggered by external Bias Temperature Stress (BTS) leads to parameter shifts and degraded device performance. This study models the trap-induced transient current in silicon carbide metal-oxide-semiconductor capacitors, providing insight into how capacitance and conductance change during C-V measurements under conditions of high temperature, varied frequency, and varied applied voltage.