Temperature dependent trap characterisation and modelling of silicon carbide MOS capacitor

Conference Paper (2024)
Author(s)

J. Li (TU Delft - Electronic Components, Technology and Materials)

S. Vollebregt (TU Delft - Electronic Components, Technology and Materials)

Y. Zhang (TU Delft - Electronic Components, Technology and Materials)

A. Shekhar (TU Delft - DC systems, Energy conversion & Storage)

Alexander May (Fraunhofer Institute for Integrated Systems and Devices Technology IISB)

Willem van Driel (TU Delft - Electronic Components, Technology and Materials)

G. Zhang (TU Delft - Electronic Components, Technology and Materials)

Research Group
Electronic Components, Technology and Materials
DOI related publication
https://doi.org/10.1109/EuroSimE60745.2024.10491433
More Info
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Publication Year
2024
Language
English
Research Group
Electronic Components, Technology and Materials
Bibliographical Note
Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.@en
ISBN (print)
979-8-3503-9364-4
ISBN (electronic)
979-8-3503-9363-7
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Abstract

Due to the deficient passivation of the interface between silicon carbide and silicon dioxide, the defect-induced capture and release of trapped charges triggered by external Bias Temperature Stress (BTS) leads to parameter shifts and degraded device performance. This study models the trap-induced transient current in silicon carbide metal-oxide-semiconductor capacitors, providing insight into how capacitance and conductance change during C-V measurements under conditions of high temperature, varied frequency, and varied applied voltage.

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