With the miniaturization and high-power requirements of microelectronic devices, the current density carried by interconnects in packaging structures continually increases and reaches the threshold of electromigration (EM) failure. In this study, we investigated the microstructure evolution and void formation in aluminum (Al) interconnects during EM at three different current densities (1/3/5 MA/cm ²) and proposed a method coupling the fully coupled theory with an optimized atomic flux divergence method. The results show as follows. First, for the interconnects in integrated circuits, current density is the main factor affecting the EM lifetime of the interconnects in a certain temperature range. With the gradual increase of current density, the contribution of thermal transfer on EM cannot be ignored. The atomic concentration gradient and stress gradient can inhibit EM failure. Second, the increase of length and the decrease of width of interconnect will lead to the increase of atomic flux inside the structure, resulting in the accumulation of voids and atoms. Third, the structure is dynamically reconstructed after deleting the atoms below the failure threshold and the simulation results agree well with the experimental results. Compared with the traditional atomic flux divergence method, the improved atomic flux divergence method based on the fully coupled theory can better fit the change trend of atomic concentration after interconnect failure, and the failure time error is reduced by about 10%.

In the domain of power electronics, especially for applications requiring high power, high temperature, and high frequency, Silicon Carbide Metal Oxide Semiconductor Field-Effect Transistors (SiC MOSFETs) stand out due to their excellent properties such as high thermal conductivity, elevated breakdown electric field, and minimal power loss. These devices are pivotal in the reliability and safety of electric vehicles, where avalanche-induced failures represent a significant risk within automotive uses. This study extensively explores the avalanche ruggedness of both planar and trench SiC MOSFET configurations through a combination of Unclamped Inductive Switching (UIS) testing in single and multiple pulse scenarios, and Technology Computer-Aided Design (TCAD) simulations. Initial UIS experiments revealed the primary failure mechanisms and their origins in SiC MOSFETs. Following empirical analysis, TCAD simulations were employed to develop comprehensive models of these devices., enhancing the understanding of failure dynamics during UIS conditions. The integration of empirical and simulation data supports the creation of advanced strategies to reduce the risk of avalanche failures, thereby enhancing the durability and reliability of Wide Bandgap Semiconductor devices.

The impact of Internet phenomena depends on how they impact users, but researchers lack visibility into how to translate Internet events into their impact. Distressingly, the research community seems to have lost hope of obtaining this information without relying on privileged viewpoints. We argue for optimism thanks to new network measurement methods and changes in Internet structure which make it possible to construct an "Internet traffic map". This map would identify the locations of users and major services, the paths between them, and the relative activity levels routed along these paths. We sketch our vision for the map, detail new measurement ideas for map construction, and identify key challenges that the research community should tackle. The realization of an Internet traffic map will be an Internet-scale research effort with Internet-scale impacts that reach far beyond the research community, and so we hope our fellow researchers are excited to join us in addressing this challenge.