Board level vibration testing is intended to assess prediction of the reliability of solder joint interconnects that are formed between electronic components and printed circuit boards (PCB). Frailties in the stress test experiment might lead to false board level reliability (BLR) evaluations. Therefore, it is essential to have a well-characterized board level vibration test method. Currently, there is no industrial test standard that prescribes board level vibration test method for electronic components at the PCB level. This paper examines the vibration test standards that are currently available in the industry and their applicability at the solder joint interconnect level. Next to that, it surveys the state-of-the-art board level vibration test setups and their impact on PCB dynamic loading and reliability at solder joint-PCB interface. It collates research on major building blocks of a board level vibration test method that includes vibration measurement techniques, PCB assemblies under test, board mounting schemes, operating environments, fault detection systems, and vibration test stress conditions that are currently used in the domain of solder joint level vibration testing. The findings from this paper are expected to reveal pitfalls and challenges while setting up board level vibration test experiments for electronic components. In addition, this paper attempts to identify research efforts that are required to make board level vibration testing a more credible means for assessing solder joint reliability. Outcomes from this study can further be used to guide future board level vibration specifications for electronic components.@en

Solder joint failure is one of the most common board-level failure modes in electronic components. It is crucial for a next-generation reliability assessment method to have an in-situ health monitoring system in place to evaluate the current state of degradation. This is achieved by specialized embedded sensors and processing the data on the edge. This study focuses on monitoring the mechanical degradation of package-to-PCB solder interconnects of a WLCSP using a high-resolution piezoresistive sensor. First, a measurement workflow was set up to optimize and significantly improve the sensor readout time. Then, utilizing a design of experiments, the test specimens were subjected to certain combinations of mechanical and thermal loads in a four-point bending setup. Temperature-coupled mechanical loading showed a greater impact on the resulting stress pattern compared to that of a superposition of the corresponding individual purely thermal and mechanical load configurations. Finally, the specimens were tested under a purely mechanical load until failure, and a correlation between the recorded stress pattern and the initiation and propagation of a crack was established.@en

Solder joint failure is one of the most common board-level failure modes in electronic components. It is crucial for a next-generation reliability assessment method to have an in-situ health monitoring system in place to evaluate the current state of degradation. This is achieved by specialized embedded sensors and processing the data on the edge. This study focuses on monitoring the mechanical degradation of package-to-PCB solder interconnects of a WLCSP using a high-resolution piezoresistive sensor. First, a measurement workflow was set up to optimize and significantly improve the sensor readout time. Then, utilizing a design of experiments, the test specimens were subjected to certain combinations of mechanical and thermal loads in a four-point bending setup. Temperature-coupled mechanical loading showed a greater impact on the resulting stress pattern compared to that of a superposition of the corresponding individual purely thermal and mechanical load configurations. Finally, the specimens were tested under a purely mechanical load until failure, and a correlation between the recorded stress pattern and the initiation and propagation of a crack was established.@en