Solder joint failure is one of the most common board-level failure modes in electronic components. It is crucial for a next-generation reliability assessment method to have an in-situ health monitoring system in place to evaluate the current state of degradation. This is achieved by specialized embedded sensors and processing the data on the edge. This study focuses on monitoring the mechanical degradation of package-to-PCB solder interconnects of a WLCSP using a high-resolution piezoresistive sensor. First, a measurement workflow was set up to optimize and significantly improve the sensor readout time. Then, utilizing a design of experiments, the test specimens were subjected to certain combinations of mechanical and thermal loads in a four-point bending setup. Temperature-coupled mechanical loading showed a greater impact on the resulting stress pattern compared to that of a superposition of the corresponding individual purely thermal and mechanical load configurations. Finally, the specimens were tested under a purely mechanical load until failure, and a correlation between the recorded stress pattern and the initiation and propagation of a crack was established.@en

Model order reduction techniques are developed and utilized to make numerical simulations more efficient. The use of Reduce Order Models (ROM) also enables data exchange with external parties without disclosing the sensitive information present in a Full-Order Model (FOM). It is crucial to optimize for both the efficiency and accuracy of a ROM to keep a minimal deviation from the FOM. The complexity of a ROM-based simulation depends on the definition of the ROM as well as its connection with the remaining FOM. This paper investigates the effect of different ROM-FOM interface definitions for a test case consisting of an electronic package-on-PCB assembly. A virtual Design of Experiments (DoE) was carried out with a total of 41 cases considering three different locations and up to four different constraint equations for the ROM-FOM interface. The effect on the accuracy and time-efficiency of the ROM-based thermomechanical simulations are compared with respect to the full Finite Element (FE) model. The deformable configuration for the interface generally showed the most accurate results, while the rigid configuration was the most efficient across the board. The beam configuration did not always follow an expected trend based on the order of elasticity values of the assigned materials. Based on the deformation results and the time associated with ROM generation and use-pass, multiple optimal solutions from the DoE are discussed.@en

Board level vibration testing is a commonly used method to predict the solder joint reliability of surface-mounted components seated onto printed circuit boards (PCB). Current board level vibration test methods are mainly developed from a solely mechanical stress application standpoint. This makes such stress tests one dimensional in nature and translation from experimentally obtained test results to the field life of components experiencing combined stress environments become ambiguous. This investigation provides insights to develop a highly accelerated vibration test approach to cover simultaneous vibration and temperature loading situations in the field. In this paper, test board layouts from the board level drop test method, JESD22-B111 (rectangular PCB), and JESD22-B111A (square PCB), prescribed by the Joint Electronic Device Engineering Council (JEDEC), are used to understand the combined stress applied to the solder interconnects. The evaluation process is carried out by means of simulations, supported by targeted experiments on ball grid array (BGA) packages with dimensions sizing from 12x12mm to 15x15mm. The results on rectangular test board assembly show reduced characteristic lifetime of solder joints when stressed under combined temperature-vibration test conditions. On the other hand, the square-shaped board type exhibits a different acceleration factor with a longer solder fatigue lifetime than that of the rectangular-shaped PCB type. Finite element simulation results complement well with this finding.

@en

Moulding compounds used for encapsulating electronics typically occupy a large portion of package volume and are most exposed to the external environment. Under harsh conditions such as high temperature, humidity, and mechanical vibrations, constituent materials of electronic components degrade, resulting in a change in their thermal, mechanical, electrical, and chemical behaviour. High-temperature ageing of electronic packages causes the oxidation of epoxy moulding compounds (EMC), forming a layer exhibiting significantly different thermomechanical properties. This reflects in the modified mechanical behaviour of the entire package, which accelerates certain failure modes and affects component reliability. Thus, it is crucial to consider gradual degenerative changes in EMC for a more accurate estimation of the component lifetime. This paper proposes a three-step modelling approach to replicate thermo-chemical changes in package encapsulation. A parametric geometry of a test package was incorporated with the ageing stage-dependent changes in thermomechanical properties of the oxidized layer. The mechanical behaviour of oxidized EMC at multiple stages of thermal ageing (at 150°C for up to 3000 hours) was first experimentally characterized and then validated using warpage measurements on thermally aged test packages and Finite Element (FE) simulations. Lastly, a trend-based interpolation of material model parameters for intermediate stages of ageing was followed, and a continuously updated degradation model (physics-based Digital Twin) was achieved. The proposed model is capable of reproducing degraded stages of the test package under thermal ageing along with its modified thermomechanical behaviour. Its limitations and significance in the domain of health monitoring of microelectronics are also discussed.@en