Design and Fabrication of a Multi-Functional Programmable Thermal Test Chip

Conference Paper (2021)
Author(s)

Romina Sattari (TU Delft - Electronic Components, Technology and Materials)

Henk van Zeijl (TU Delft - Electronic Components, Technology and Materials)

Guo Qi Zhang (TU Delft - Electronic Components, Technology and Materials)

Research Group
Electronic Components, Technology and Materials
Copyright
© 2021 R. Sattari, H.W. van Zeijl, Kouchi Zhang
DOI related publication
https://doi.org/10.23919/EMPC53418.2021.9584984
More Info
expand_more
Publication Year
2021
Language
English
Copyright
© 2021 R. Sattari, H.W. van Zeijl, Kouchi Zhang
Research Group
Electronic Components, Technology and Materials
Pages (from-to)
1-7
ISBN (print)
978-1-6654-2368-7
ISBN (electronic)
978-0-9568086-7-7
Reuse Rights

Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons.

Abstract

This paper focuses on the design and fabrication of a new programmable thermal test chip as a flexible and cost-effective solution for simplification of characterization/prototyping of new packages. The cell-based design format makes the chip fit into any modular array configuration. One unit cell is as small as 4x4 mm2, including 6 individually programmable micro-heaters and 3 resistance temperature detectors (RTDs). All micro-heaters and sensors have 4-point Kelvin connections for improved measurement accuracy. The chip contains 2 metal layers: 100 nm thin-film Titanium to create micro-heaters and RTDs, and 2 μm Aluminum to add single bump measurement units and daisy chain connections. These structures facilitate bump reliability investigations during thermal/power cycling tests in flip-chip assembly technology. The calibration curves of RTDs show a sensitivity of 12 $\Omega$/K which is improved by 50 percent compared to the state-of-the-art TTC. The proposed design provides higher spatial resolution in thermal mapping by accommodating 3 RTDs per cell. The dense configuration of micro-heaters increases the uniformity of the power dissipation, which enhances the accuracy of thermal interface material (TIM) characterizations. The steady-state infrared (IR) thermography of a 20x20 mm2 TTC, including 150 active micro-heaters, verifies the promising uniformity of the heat profile over the chip surface.

Files

Romina_Sattari_EMPC2021.pdf
(pdf | 16.2 Mb)
License info not available