IN [1], there is a mistake in the timing diagram shown in Fig. 6. Switches S 1-S 4 are skipping some of the samples and the rate at which they are operating implies a TDM rate of 10 MHz, whereas (as described in [1]) this should be 20 MHz. In the updated Fig. 6, S 1-S 4 have been updated and a minor change has been made to the timing shown for switches Q₁ and Q₂, such that the correct TDM rate is indicated and no sample provided to the S/H stage via N1-N4 is skipped in the diagram. (Figure presented).

Intra-cardiac echography (ICE) probes (Fig. 32.2.1) are widely used in electrophysiology for their good procedure guidance and relatively safe application. ASICs are increasingly employed in these miniature probes to enhance signal quality and reduce the number of connections needed in mm-diameter catheters [1]-[5]. 3D visualization in real-time is additionally enabled by 2D transducer arrays with, for each transducer element, a high-voltage (HV) transmit (TX) part, to generate acoustic pulses of sufficient pressure, and a receive (RX) path, to process the resulting echoes. To achieve the required reduction in RX channels, micro-beamforming (BF), which merges the signals from a subarray using a delay-and-sum operation, has been shown to be an effective solution [3], [4]. However, due to the frame-rate reduction that is associated with BF, these designs cannot serve emerging high-frame-rate imaging modes (1000 volumes/s) like 3D blood-flow and elastography imaging. In-probe digitization has recently been investigated to provide further channel-count reduction, make data transmission more robust, and enable pre-processing in the probe [1]-[3]. However, these earlier designs have either no TX functionality [2], [3] or only low-voltage (LV) TX [1] integrated. Combining BF and digitization with area-hungry HV transmitters in a pitch-matched scalable fashion while supporting high-frame-rate imaging remains an unmet challenge. The work presented in this paper meets this target, enabled by a hybrid ADC, the small die size of which allows for co-integration with 65V element-level pulsers.

This paper presents an ultrasound receiver ASIC in 180nm CMOS that enables element-level digitization of echo signals in miniature 3D ultrasound probes. It is the first to integrate an analog front-end and a 10-b Nyquist ADC within the 150 μ m element pitch of a 5-MHz 2D transducer array. To achieve this, a hybrid SAR/shared-single-slope architecture is proposed in which the ramp generator is shared within each 2 × 2 subarray. The ASIC consumes 1.54mW/element and has been successfully demonstrated in an acoustic imaging experiment.

This paper presents the design, fabrication and characterization of a miniature PZT-on-CMOS matrix transducer for real-time pediatric 3-dimensional (3D) transesophageal echocardiography (TEE). This 3D TEE probe consists of a 32 × 32 array of PZT elements integrated on top of an Application Specific Integrated Circuit (ASIC). We propose a partitioned transmit/receive array architecture wherein the 8 × 8 transmitter elements, located at the centre of the array, are directly wired out and the remaining receive elements are grouped into 96 sub-arrays of 3 × 3 elements. The echoes received by these sub-groups are locally processed by micro-beamformer circuits in the ASIC that allow pre-steering up to ±37°. The PZT-on-CMOS matrix transducer has been characterized acoustically and has a centre frequency of 5.8 MHz, -6 dB bandwidth of 67%, a transmit efficiency of 6 kPa/V at 30 mm, and a receive dynamic range of 85 dB with minimum and maximum detectable pressures of 5 Pa and 84 kPa respectively. The properties are very suitable for a miniature pediatric real-time 3D TEE probe.

Until now, no matrix transducer has been realized for 3D transesophageal echocardiography (TEE) in pediatric patients. In 3D TEE with a matrix transducer, the biggest challenges are to connect a large number of elements to a standard ultrasound system, and to achieve a high volume rate (>200 Hz). To address these issues, we have recently developed a prototype miniaturized matrix transducer for pediatric patients with micro-beamforming and a small central transmitter. In this paper we propose two multiline parallel 3D beamforming techniques (μBF25 and μBF169) using the micro-beamformed datasets from 25 and 169 transmit events to achieve volume rates of 300 Hz and 44 Hz, respectively. Both the realizations use angle-weighted combination of the neighboring overlapping sub-volumes to avoid artifacts due to sharp intensity changes introduced by parallel beamforming. In simulation, the image quality in terms of the width of the point spread function (PSF), lateral shift invariance and mean clutter level for volumes produced by μBF25 and μBF169 are similar to the idealized beamforming using a conventional single-line acquisition with a fully-sampled matrix transducer (FS4k, 4225 transmit events). For completeness, we also investigated a 9 transmit-scheme (3 × 3) that allows even higher frame rates but found worse B-mode image quality with our probe. The simulations were experimentally verified by acquiring the μBF datasets from the prototype using a Verasonics V1 research ultrasound system. For both μBF169 and μBF25, the experimental PSFs were similar to the simulated PSFs, but in the experimental PSFs, the clutter level was ∼10 dB higher. Results indicate that the proposed multiline 3D beamforming techniques with the prototype matrix transducer are promising candidates for real-time pediatric 3D TEE.

This paper presents a front-end application-specified integrated circuit (ASIC) integrated with a 2-D PZT matrix transducer that enables in-probe digitization with acceptable power dissipation for the next-generation endoscopic and catheter-based 3-D ultrasound imaging systems. To achieve power-efficient massively parallel analog-to-digital conversion (ADC) in a 2-D array, a 10-bit 30 MS/s beamforming ADC that merges the subarray beamforming and digitization functions in the charge domain is proposed. It eliminates the need for costly intermediate buffers, thus significantly reducing both power consumption and silicon area. Self-calibrated charge references are implemented in each subarray to further optimize the system-level power efficiency. High-speed datalinks are employed in combination with the subarray beamforming scheme to realize a 36-fold channel-count reduction and an aggregate output data rate of 6 Gb/s for a prototype receive array of 24 x 6 elements. The ASIC achieves a record power efficiency of 0.91 mW/element during receive. Its functionality has been demonstrated in both electrical and acoustic imaging experiments.

Intravascular ultrasound is an imaging modality used to visualize atherosclerosis from within the inner lumen of human arteries. Complex lesions like chronic total occlusions require forward-looking intravascular ultrasound (FL-IVUS), instead of the conventional side-looking geometry. Volumetric imaging can be achieved with 2D array transducers, which present major challenges in reducing cable count and device integration. In this work we present an 80-element lead zirconium titanate (PZT) matrix ultrasound transducer for FL-IVUS imaging with a front-end application-specific integrated circuit (ASIC) requiring only 4 cables. After investigating optimal transducer designs we fabricated the matrix transducer consisting of 16 transmit (TX) and 64 receive (RX) elements arranged on top of an ASIC having an outer diameter of 1.5 mm and a central hole of 0.5 mm for a guidewire. We modeled the transducer using finite element analysis and compared the simulation results to the values obtained through acoustic measurements. The TX elements showed uniform behavior with a center frequency of 14 MHz, a -3 dB bandwidth of 44 % and a transmit sensitivity of 0.4 kPa/V at 6 mm. The RX elements showed center frequency and bandwidth similar to the TX elements, with an estimated receive sensitivity of 3.7 μV/Pa. We successfully acquired a 3D FL image of three spherical reflectors in water using delay-and-sum beamforming and the coherence factor method. Full synthetic aperture acquisition can be achieved with frame rates on the order of 100 Hz. The acoustic characterization and the initial imaging results show the potential of the proposed transducer to achieve 3D FL-IVUS imaging.

This paper presents an area- and power-efficient application-specified integrated circuit (ASIC) for 3-D forward-looking intravascular ultrasound imaging. The ASIC is intended to be mounted at the tip of a catheter, and has a circular active area with a diameter of 1.5 mm on the top of which a 2-D array of piezoelectric transducer elements is integrated. It requires only four micro-coaxial cables to interface 64 receive (RX) elements and 16 transmit (TX) elements with an imaging system. To do so, it routes high-voltage (HV) pulses generated by the system to selected TX elements using compact HV switch circuits, digitizes the resulting echo signal received by a selected RX element locally, and employs an energy-efficient load-modulation datalink to return the digitized echo signal to the system in a robust manner. A multi-functional command line provides the required sampling clock, configuration data, and supply voltage for the HV switches. The ASIC has been realized in a 0.18-μm HV CMOS technology and consumes only 9.1 mW. Electrical measurements show 28-V HV switching and RX digitization with a 16-MHz bandwidth and 53-dB dynamic range. Acoustical measurements demonstrate successful pulse transmission and reception. Finally, a 3-D ultrasound image of a three-needle phantom is generated to demonstrate the imaging capability.

This paper presents a power-and area-efficient front-end application-specific integrated circuit (ASIC) that is directly integrated with an array of 32 × 32 piezoelectric transducer elements to enable next-generation miniature ultrasound probes for real-time 3-D transesophageal echocardiography. The 6.1 × 6.1 mm² ASIC, implemented in a low-voltage 0.18-μm CMOS process, effectively reduces the number of receive (RX) cables required in the probe's narrow shaft by ninefold with the aid of 96 delay-and-sum beamformers, each of which locally combines the signals received by a sub-array of 3 × 3 elements. These beamformers are based on pipeline-operated analog sample-and-hold stages and employ a mismatch-scrambling technique to prevent the ripple signal associated with the mismatch between these stages from limiting the dynamic range. In addition, an ultralow-power low-noise amplifier architecture is proposed to increase the power efficiency of the RX circuitry. The ASIC has a compact element matched layout and consumes only 0.27 mW/channel while receiving, which is lower than the state-of-the-art circuit. Its functionality has been successfully demonstrated in 3-D imaging experiments.

This paper presents a front-end ASIC for forward-looking intravascular ultrasound (IVUS) imaging. The ASIC is intended to be mounted at the tip of a catheter and can interface a total of 80 piezo-electric transducer elements with an imaging systems using only 4 cables, thus significantly reducing the system complexity compared to the prior art. It is capable of switching high-voltage transmit pulses to 16 transmit elements, and capturing the resulting echo signals using 64 multiplexed receive elements. The ASIC digitizes the received signals locally, providing more robust communication than prior analog approaches. Measurements show that the ASIC effectively switches transmit pulses up to 30 V, and digitizes echo signals with a bandwidth of 16 MHz, while consuming only 10 mW. Acoustic measurements in combination with a prototype transducer array demonstrate pulse transmission and reception. Finally, a B-mode image of a needle phantom demonstrates the imaging capability.