A Front-End ASIC with Receive Sub-array Beamforming Integrated with a 32 × 32 PZT Matrix Transducer for 3-D Transesophageal Echocardiography

Journal article (2017)

Authors

C. Chen Electronic Instrumentation - EEMCS
Z. Chen Electronic Instrumentation - EEMCS
J.G. Bosch Erasmus MC
M.D. Verweij , Erasmus MC
N. de Jong Erasmus MC,
M.A.P. Pertijs Electronic Instrumentation - EEMCS
Deep Bera Erasmus MC
Z.Y. Chang Electronic Instrumentation - EEMCS
Jacco Ponte Oldelft Ultrasound
Christian Prins Oldelft Ultrasound
H.J. Vos Erasmus MC,
Research Group
Electronic Instrumentation (EEMCS) (TU Delft)
Copyright: © 2017 C. Chen, Z. Chen, Deep Bera, S.B. Raghunathan, M. Shabanimotlagh, E.C. Noothout, Z.Y. Chang, Jacco Ponte, Christian Prins, H.J. Vos, J.G. Bosch, M.D. Verweij, N. de Jong, M.A.P. Pertijs
DOI
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https://doi.org/10.1109/JSSC.2016.2638433
Matrix transducer arrays Sub-array beamforming Ultrasound application-specific integrated circuit (ASIC) 3-D ultrasound imaging Transesophageal echocardiography (TEE)
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Published Date

01-04-2017

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronic Instrumentation

Abstract

This paper presents a power-and area-efficient front-end application-specific integrated circuit (ASIC) that is directly integrated with an array of 32 × 32 piezoelectric transducer elements to enable next-generation miniature ultrasound probes for real-time 3-D transesophageal echocardiography. The 6.1 × 6.1 mm2 ASIC, implemented in a low-voltage 0.18-μm CMOS process, effectively reduces the number of receive (RX) cables required in the probe's narrow shaft by ninefold with the aid of 96 delay-and-sum beamformers, each of which locally combines the signals received by a sub-array of 3 × 3 elements. These beamformers are based on pipeline-operated analog sample-and-hold stages and employ a mismatch-scrambling technique to prevent the ripple signal associated with the mismatch between these stages from limiting the dynamic range. In addition, an ultralow-power low-noise amplifier architecture is proposed to increase the power efficiency of the RX circuitry. The ASIC has a compact element matched layout and consumes only 0.27 mW/channel while receiving, which is lower than the state-of-the-art circuit. Its functionality has been successfully demonstrated in 3-D imaging experiments.