A Front-End ASIC with Receive Sub-array Beamforming Integrated with a 32 × 32 PZT Matrix Transducer for 3-D Transesophageal Echocardiography

Journal Article (2017)
Author(s)

Chao Chen (TU Delft - Electronic Instrumentation)

Zhao Chen (TU Delft - Electronic Instrumentation)

Deep Bera (Erasmus MC)

Shreyas B. Raghunathan (ImPhys/Acoustical Wavefield Imaging )

Maysam Shabanimotlagh (ImPhys/Acoustical Wavefield Imaging )

Emile Noothout (ImPhys/Acoustical Wavefield Imaging )

Zu-Yao Chang (TU Delft - Electronic Instrumentation)

Jacco Ponte (Oldelft Ultrasound)

Christian Prins (Oldelft Ultrasound)

Hendrik J. Vos (ImPhys/Acoustical Wavefield Imaging , Erasmus MC)

Johan G. Bosch (Erasmus MC)

Martin D. Verweij (Erasmus MC, ImPhys/Acoustical Wavefield Imaging )

Nico De Jong (Erasmus MC, ImPhys/Acoustical Wavefield Imaging )

Michiel A.P. Pertijs (TU Delft - Electronic Instrumentation)

DOI related publication
https://doi.org/10.1109/JSSC.2016.2638433 Final published version
More Info
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Publication Year
2017
Language
English
Journal title
IEEE Journal of Solid State Circuits
Issue number
4
Volume number
52
Article number
7807320
Pages (from-to)
994-1006
Downloads counter
151
Collections
Institutional Repository
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Abstract

This paper presents a power-and area-efficient front-end application-specific integrated circuit (ASIC) that is directly integrated with an array of 32 × 32 piezoelectric transducer elements to enable next-generation miniature ultrasound probes for real-time 3-D transesophageal echocardiography. The 6.1 × 6.1 mm2 ASIC, implemented in a low-voltage 0.18-μm CMOS process, effectively reduces the number of receive (RX) cables required in the probe's narrow shaft by ninefold with the aid of 96 delay-and-sum beamformers, each of which locally combines the signals received by a sub-array of 3 × 3 elements. These beamformers are based on pipeline-operated analog sample-and-hold stages and employ a mismatch-scrambling technique to prevent the ripple signal associated with the mismatch between these stages from limiting the dynamic range. In addition, an ultralow-power low-noise amplifier architecture is proposed to increase the power efficiency of the RX circuitry. The ASIC has a compact element matched layout and consumes only 0.27 mW/channel while receiving, which is lower than the state-of-the-art circuit. Its functionality has been successfully demonstrated in 3-D imaging experiments.

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