Correction to: Nature Energyhttps://doi.org/10.1038/s41560-023-01414-5, published online 3 January 2024. In the version of this article initially published, lithium (green, “Li”) and sodium (purple, “Na”) color key labels in Fig. 3a,d,e were interchanged and are now amended in the HTML and PDF versions of the article.

This article presents an application-specific integrated circuit (ASIC) for battery-powered ultrasound (US) devices. The ASIC implements a novel energy-efficient high-voltage (HV) pulser that generates HV transmit (TX) pulses directly from a low-voltage (LV) battery supply. By means of a single off-chip inductor, energy is supplied to a US transducer in a resonant fashion, directly generating half-period sinusoidal HV pulses on the transducer, while consuming substantially less energy than a conventional class-D pulser. By recycling residual reactive energy from the transducer back to the input, the energy consumption is further reduced by more than 50%. The autocalibration techniques are leveraged to deal with tolerances of the inductor, transducer, and battery supply and thus maximize the energy efficiency. A prototype chip was fabricated in TSMC 0.18-μm HV BCD technology and used to drive external 120-pF capacitive micromachined US transducers (CMUTs) with a center frequency of approximately 2.5 MHz. Electrical measurements show that the prototype can generate pulses with a peak amplitude between 10 and 30 V accurate to within ±1 V. Acoustic measurements demonstrate successful ultrasonic pulse transmission and pulse-echo measurements. The prototype reaches a peak efficiency of 0.23 fCV ² , which is the highest reported to date for HV pulsers targeting US imaging.

This article quantitatively analyzes the impact of bit errors in digitized RF data on ultrasound image quality. The quality of B-mode images in both linear array and phased array imaging is evaluated by means of three objective image quality metrics: peak signal-to-noise ratio, structural similarity index, and contrast-to-noise ratio, when bit errors are introduced to the RF data with different bit-error rates (BERs). The effectiveness of coding schemes for forward error detection and correction to improve the image quality is also studied. The results show that ultrasound imaging is inherently resilient to high BER. The image quality suffers unnoticeable degradation for BER lower than 1E-6. Simple 1-bit parity coding with 9% added redundancy helps to retain similar image quality for BER up to 1E-4, and Hamming coding with 33.3% added redundancy allows the BER to increase to 1E-3. These results can serve as a guideline in the datalink design for ultrasound probes with in-probe receive digitization. With much more relaxed BER requirements than in typical datalinks, the design can be optimized by allowing fewer cables with higher data rate per cable or lower power consumption with the same cable count.

This paper presents an ultrasound receiver ASIC in 180nm CMOS that enables element-level digitization of echo signals in miniature 3D ultrasound probes. It is the first to integrate an analog front-end and a 10-b Nyquist ADC within the 150 μ m element pitch of a 5-MHz 2D transducer array. To achieve this, a hybrid SAR/shared-single-slope architecture is proposed in which the ramp generator is shared within each 2 × 2 subarray. The ASIC consumes 1.54mW/element and has been successfully demonstrated in an acoustic imaging experiment.

This paper presents the design, fabrication and characterization of a miniature PZT-on-CMOS matrix transducer for real-time pediatric 3-dimensional (3D) transesophageal echocardiography (TEE). This 3D TEE probe consists of a 32 × 32 array of PZT elements integrated on top of an Application Specific Integrated Circuit (ASIC). We propose a partitioned transmit/receive array architecture wherein the 8 × 8 transmitter elements, located at the centre of the array, are directly wired out and the remaining receive elements are grouped into 96 sub-arrays of 3 × 3 elements. The echoes received by these sub-groups are locally processed by micro-beamformer circuits in the ASIC that allow pre-steering up to ±37°. The PZT-on-CMOS matrix transducer has been characterized acoustically and has a centre frequency of 5.8 MHz, -6 dB bandwidth of 67%, a transmit efficiency of 6 kPa/V at 30 mm, and a receive dynamic range of 85 dB with minimum and maximum detectable pressures of 5 Pa and 84 kPa respectively. The properties are very suitable for a miniature pediatric real-time 3D TEE probe.

Intravascular ultrasound is an imaging modality used to visualize atherosclerosis from within the inner lumen of human arteries. Complex lesions like chronic total occlusions require forward-looking intravascular ultrasound (FL-IVUS), instead of the conventional side-looking geometry. Volumetric imaging can be achieved with 2D array transducers, which present major challenges in reducing cable count and device integration. In this work we present an 80-element lead zirconium titanate (PZT) matrix ultrasound transducer for FL-IVUS imaging with a front-end application-specific integrated circuit (ASIC) requiring only 4 cables. After investigating optimal transducer designs we fabricated the matrix transducer consisting of 16 transmit (TX) and 64 receive (RX) elements arranged on top of an ASIC having an outer diameter of 1.5 mm and a central hole of 0.5 mm for a guidewire. We modeled the transducer using finite element analysis and compared the simulation results to the values obtained through acoustic measurements. The TX elements showed uniform behavior with a center frequency of 14 MHz, a -3 dB bandwidth of 44 % and a transmit sensitivity of 0.4 kPa/V at 6 mm. The RX elements showed center frequency and bandwidth similar to the TX elements, with an estimated receive sensitivity of 3.7 μV/Pa. We successfully acquired a 3D FL image of three spherical reflectors in water using delay-and-sum beamforming and the coherence factor method. Full synthetic aperture acquisition can be achieved with frame rates on the order of 100 Hz. The acoustic characterization and the initial imaging results show the potential of the proposed transducer to achieve 3D FL-IVUS imaging.

This paper presents an area- and power-efficient application-specified integrated circuit (ASIC) for 3-D forward-looking intravascular ultrasound imaging. The ASIC is intended to be mounted at the tip of a catheter, and has a circular active area with a diameter of 1.5 mm on the top of which a 2-D array of piezoelectric transducer elements is integrated. It requires only four micro-coaxial cables to interface 64 receive (RX) elements and 16 transmit (TX) elements with an imaging system. To do so, it routes high-voltage (HV) pulses generated by the system to selected TX elements using compact HV switch circuits, digitizes the resulting echo signal received by a selected RX element locally, and employs an energy-efficient load-modulation datalink to return the digitized echo signal to the system in a robust manner. A multi-functional command line provides the required sampling clock, configuration data, and supply voltage for the HV switches. The ASIC has been realized in a 0.18-μm HV CMOS technology and consumes only 9.1 mW. Electrical measurements show 28-V HV switching and RX digitization with a 16-MHz bandwidth and 53-dB dynamic range. Acoustical measurements demonstrate successful pulse transmission and reception. Finally, a 3-D ultrasound image of a three-needle phantom is generated to demonstrate the imaging capability.

This paper presents a front-end application-specified integrated circuit (ASIC) integrated with a 2-D PZT matrix transducer that enables in-probe digitization with acceptable power dissipation for the next-generation endoscopic and catheter-based 3-D ultrasound imaging systems. To achieve power-efficient massively parallel analog-to-digital conversion (ADC) in a 2-D array, a 10-bit 30 MS/s beamforming ADC that merges the subarray beamforming and digitization functions in the charge domain is proposed. It eliminates the need for costly intermediate buffers, thus significantly reducing both power consumption and silicon area. Self-calibrated charge references are implemented in each subarray to further optimize the system-level power efficiency. High-speed datalinks are employed in combination with the subarray beamforming scheme to realize a 36-fold channel-count reduction and an aggregate output data rate of 6 Gb/s for a prototype receive array of 24 x 6 elements. The ASIC achieves a record power efficiency of 0.91 mW/element during receive. Its functionality has been demonstrated in both electrical and acoustic imaging experiments.

Until now, no matrix transducer has been realized for 3D transesophageal echocardiography (TEE) in pediatric patients. In 3D TEE with a matrix transducer, the biggest challenges are to connect a large number of elements to a standard ultrasound system, and to achieve a high volume rate (>200 Hz). To address these issues, we have recently developed a prototype miniaturized matrix transducer for pediatric patients with micro-beamforming and a small central transmitter. In this paper we propose two multiline parallel 3D beamforming techniques (μBF25 and μBF169) using the micro-beamformed datasets from 25 and 169 transmit events to achieve volume rates of 300 Hz and 44 Hz, respectively. Both the realizations use angle-weighted combination of the neighboring overlapping sub-volumes to avoid artifacts due to sharp intensity changes introduced by parallel beamforming. In simulation, the image quality in terms of the width of the point spread function (PSF), lateral shift invariance and mean clutter level for volumes produced by μBF25 and μBF169 are similar to the idealized beamforming using a conventional single-line acquisition with a fully-sampled matrix transducer (FS4k, 4225 transmit events). For completeness, we also investigated a 9 transmit-scheme (3 × 3) that allows even higher frame rates but found worse B-mode image quality with our probe. The simulations were experimentally verified by acquiring the μBF datasets from the prototype using a Verasonics V1 research ultrasound system. For both μBF169 and μBF25, the experimental PSFs were similar to the simulated PSFs, but in the experimental PSFs, the clutter level was ∼10 dB higher. Results indicate that the proposed multiline 3D beamforming techniques with the prototype matrix transducer are promising candidates for real-time pediatric 3D TEE.

This paper presents a power-and area-efficient front-end application-specific integrated circuit (ASIC) that is directly integrated with an array of 32 × 32 piezoelectric transducer elements to enable next-generation miniature ultrasound probes for real-time 3-D transesophageal echocardiography. The 6.1 × 6.1 mm² ASIC, implemented in a low-voltage 0.18-μm CMOS process, effectively reduces the number of receive (RX) cables required in the probe's narrow shaft by ninefold with the aid of 96 delay-and-sum beamformers, each of which locally combines the signals received by a sub-array of 3 × 3 elements. These beamformers are based on pipeline-operated analog sample-and-hold stages and employ a mismatch-scrambling technique to prevent the ripple signal associated with the mismatch between these stages from limiting the dynamic range. In addition, an ultralow-power low-noise amplifier architecture is proposed to increase the power efficiency of the RX circuitry. The ASIC has a compact element matched layout and consumes only 0.27 mW/channel while receiving, which is lower than the state-of-the-art circuit. Its functionality has been successfully demonstrated in 3-D imaging experiments.

Data acquisition from 2-D transducer arrays has become one of the main challenges for the development of endoscopic and catheter-based 3-D ultrasound imaging devices. Front-end ASICs with sub-array pre-beamforming have been reported that reduce the cable number by an order of magnitude. Further channel reduction requires digitization in the front-end ASIC to facilitate more in-probe data processing functions. Prior solutions, however, are too large and power-hungry to be integrated in a miniature ultrasound probe. In this work, we present a front-end ASIC with an element-pitch-matched layout that combines sub-array beamforming, digitization and high-speed data transmission. It achieves a 36-fold channel-count reduction and a record power-efficiency with less than 1 mW/element power dissipation in receive.

This paper presents a front-end ASIC for forward-looking intravascular ultrasound (IVUS) imaging. The ASIC is intended to be mounted at the tip of a catheter and can interface a total of 80 piezo-electric transducer elements with an imaging systems using only 4 cables, thus significantly reducing the system complexity compared to the prior art. It is capable of switching high-voltage transmit pulses to 16 transmit elements, and capturing the resulting echo signals using 64 multiplexed receive elements. The ASIC digitizes the received signals locally, providing more robust communication than prior analog approaches. Measurements show that the ASIC effectively switches transmit pulses up to 30 V, and digitizes echo signals with a bandwidth of 16 MHz, while consuming only 10 mW. Acoustic measurements in combination with a prototype transducer array demonstrate pulse transmission and reception. Finally, a B-mode image of a needle phantom demonstrates the imaging capability.

This paper presents a front-end application-specific integrated circuit (ASIC) that demonstrates the feasibility of inprobe digitization for next-generation miniature 3-D ultrasound probes with acceptable power- and area-efficiency. The proposed design employs a low-power charge-domain ADC that is directly merged with the sample-and-hold delay lines in each subarray, and high-speed datalinks at the ASIC periphery to realize an additional channel-count reduction compared to prior work based on analog subarray beamforming. The 4.8 × 2 mm² ASIC, which has a compact layout element-matched to a 5-MHz 150-μm-pitch PZT matrix transducer, achieves an overall 36-fold channel-count reduction and a state-of-the-art power-efficiency with less than 1 mW/element power dissipation while receiving, which is acceptable even when scaled up to a 1000-element probe. The prototype ASIC has been fabricated in a 0.18 μm CMOS process. Its functionality has been successfully evaluated with both electrical and acoustical measurements.